Read the Docs build information Build id: 2760360 Project: openhw-group-cva6-user-manual Version: latest Commit: fb4a8d4472f9140fbac5b3b1ec9cea65a48b24d9 Date: 2025-01-26T20:51:27.152237Z State: finished Success: True [rtd-command-info] start-time: 2025-01-26T20:51:28.189214Z, end-time: 2025-01-26T20:51:29.316808Z, duration: 1, exit-code: 0 git clone --depth 1 https://github.com/openhwgroup/cva6.git . Cloning into '.'... [rtd-command-info] start-time: 2025-01-26T20:51:29.381193Z, end-time: 2025-01-26T20:51:30.346691Z, duration: 0, exit-code: 0 git fetch origin --force --prune --prune-tags --depth 50 refs/heads/master:refs/remotes/origin/master From https://github.com/openhwgroup/cva6 * [new tag] v5.2.0 -> v5.2.0 [rtd-command-info] start-time: 2025-01-26T20:51:30.468954Z, end-time: 2025-01-26T20:51:30.752877Z, duration: 0, exit-code: 0 git checkout --force origin/master Note: switching to 'origin/master'. You are in 'detached HEAD' state. You can look around, make experimental changes and commit them, and you can discard any commits you make in this state without impacting any branches by switching back to a branch. If you want to create a new branch to retain commits you create, you may do so (now or later) by using -c with the switch command. Example: git switch -c Or undo this operation with: git switch - Turn off this advice by setting config variable advice.detachedHead to false HEAD is now at fb4a8d4 Fix missing parametrization in performance counters (#2740) [rtd-command-info] start-time: 2025-01-26T20:51:30.817613Z, end-time: 2025-01-26T20:51:30.868142Z, duration: 0, exit-code: 0 cat .readthedocs.yaml # Configuration file for ReadTheDocs, used to render the CVA6 # User Manual to https://docs.openhwgroup.org/projects/cva6-user-manual. # SPDX-License-Identifier:Apache-2.0 WITH SHL-2.1 version: 2 submodules: include: - docs/riscv-isa/riscv-isa-manual recursive: true build: os: "ubuntu-20.04" tools: python: "3.9" nodejs: "20" ruby: "3.3" apt_packages: - cmake - bison - flex - libpango1.0-dev - libgdk-pixbuf2.0-0 - libgtk2.0-dev jobs: post_install: - npm install docs/riscv-isa/riscv-isa-manual/dependencies - gem install -g docs/riscv-isa/riscv-isa-manual/dependencies/Gemfile pre_build: - PATH=$PWD/node_modules/.bin:$PATH make -C docs prepare # Build from the docs directory with Sphinx sphinx: configuration: docs/conf.py # Explicitly set the Python requirements python: install: - requirements: docs/requirements.txt [rtd-command-info] start-time: 2025-01-26T20:51:30.984556Z, end-time: 2025-01-26T20:51:31.137221Z, duration: 0, exit-code: 0 git submodule sync [rtd-command-info] start-time: 2025-01-26T20:51:31.200403Z, end-time: 2025-01-26T20:51:34.589288Z, duration: 3, exit-code: 0 git submodule update --init --force --recursive -- docs/riscv-isa/riscv-isa-manual Submodule 'docs/06_cv32a65x_riscv/riscv-isa-manual' (https://github.com/riscv/riscv-isa-manual.git) registered for path 'docs/riscv-isa/riscv-isa-manual' Cloning into '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/riscv-isa/riscv-isa-manual'... Submodule path 'docs/riscv-isa/riscv-isa-manual': checked out '4f277ff8ea8c0fc9394dfccd1da0ace34b1aef68' Submodule 'docs-resources' (https://github.com/riscv/docs-resources) registered for path 'docs/riscv-isa/riscv-isa-manual/docs-resources' Cloning into '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/riscv-isa/riscv-isa-manual/docs-resources'... Submodule path 'docs/riscv-isa/riscv-isa-manual/docs-resources': checked out 'a76dd1d390cba28e3b1ce86313af03ce9b69399d' [rtd-command-info] start-time: 2025-01-26T20:51:35.519447Z, end-time: 2025-01-26T20:51:45.648252Z, duration: 10, exit-code: 0 apt-get update --assume-yes --quiet Hit:1 http://archive.ubuntu.com/ubuntu focal InRelease Get:2 http://security.ubuntu.com/ubuntu focal-security InRelease [128 kB] Get:3 http://archive.ubuntu.com/ubuntu focal-updates InRelease [128 kB] Get:4 http://archive.ubuntu.com/ubuntu focal-backports InRelease [128 kB] Get:5 http://archive.ubuntu.com/ubuntu focal-updates/restricted amd64 Packages [4463 kB] Get:6 http://security.ubuntu.com/ubuntu focal-security/restricted amd64 Packages [4276 kB] Get:7 http://archive.ubuntu.com/ubuntu focal-updates/multiverse amd64 Packages [34.6 kB] Get:8 http://archive.ubuntu.com/ubuntu focal-updates/universe amd64 Packages [1589 kB] Get:9 http://archive.ubuntu.com/ubuntu focal-updates/main amd64 Packages [4663 kB] Get:10 http://security.ubuntu.com/ubuntu focal-security/multiverse amd64 Packages [30.9 kB] Get:11 http://security.ubuntu.com/ubuntu focal-security/universe amd64 Packages [1297 kB] Get:12 http://security.ubuntu.com/ubuntu focal-security/main amd64 Packages [4187 kB] Fetched 20.9 MB in 3s (7368 kB/s) Reading package lists... [rtd-command-info] start-time: 2025-01-26T20:51:45.717919Z, end-time: 2025-01-26T20:52:35.285392Z, duration: 49, exit-code: 0 apt-get install --assume-yes --quiet -- cmake bison flex libpango1.0-dev libgdk-pixbuf2.0-0 libgtk2.0-dev Reading package lists... Building dependency tree... Reading state information... The following additional packages will be installed: autopoint bsdmainutils cmake-data debhelper dh-autoreconf dh-strip-nondeterminism dwz gettext gettext-base gir1.2-atk-1.0 gir1.2-freedesktop gir1.2-gdkpixbuf-2.0 gir1.2-gtk-2.0 gir1.2-harfbuzz-0.0 gir1.2-pango-1.0 groff-base intltool-debian libarchive-cpio-perl libarchive-zip-perl libarchive13 libatk1.0-dev libcroco3 libdatrie-dev libdebhelper-perl libfile-stripnondeterminism-perl libfl-dev libfl2 libfribidi-dev libgail-common libgail18 libgdk-pixbuf2.0-bin libgdk-pixbuf2.0-common libgdk-pixbuf2.0-dev libgraphite2-dev libgtk2.0-0 libgtk2.0-bin libharfbuzz-dev libharfbuzz-gobject0 libjsoncpp1 libltdl-dev libpangoxft-1.0-0 librhash0 libsub-override-perl libthai-dev libtool libuchardet0 libuv1 libxcomposite-dev libxcursor-dev libxdamage-dev libxfixes-dev libxi-dev libxinerama-dev libxml2-utils libxrandr-dev man-db pango1.0-tools po-debconf x11proto-input-dev x11proto-randr-dev x11proto-xinerama-dev Suggested packages: bison-doc wamerican | wordlist whois vacation cmake-doc ninja-build dh-make flex-doc gettext-doc libasprintf-dev libgettextpo-dev groff lrzip libdatrie-doc libgraphite2-utils gvfs libgtk2.0-doc libtool-doc libpango1.0-doc libthai-doc gfortran | fortran95-compiler gcj-jdk apparmor www-browser libmail-box-perl The following NEW packages will be installed: autopoint bison bsdmainutils cmake cmake-data debhelper dh-autoreconf dh-strip-nondeterminism dwz flex gettext gettext-base gir1.2-atk-1.0 gir1.2-freedesktop gir1.2-gdkpixbuf-2.0 gir1.2-gtk-2.0 gir1.2-harfbuzz-0.0 gir1.2-pango-1.0 groff-base intltool-debian libarchive-cpio-perl libarchive-zip-perl libarchive13 libatk1.0-dev libcroco3 libdatrie-dev libdebhelper-perl libfile-stripnondeterminism-perl libfl-dev libfl2 libfribidi-dev libgdk-pixbuf2.0-dev libgraphite2-dev libgtk2.0-dev libharfbuzz-dev libharfbuzz-gobject0 libjsoncpp1 libltdl-dev libpango1.0-dev libpangoxft-1.0-0 librhash0 libsub-override-perl libthai-dev libtool libuchardet0 libuv1 libxcomposite-dev libxcursor-dev libxdamage-dev libxfixes-dev libxi-dev libxinerama-dev libxml2-utils libxrandr-dev man-db pango1.0-tools po-debconf x11proto-input-dev x11proto-randr-dev x11proto-xinerama-dev The following packages will be upgraded: libgail-common libgail18 libgdk-pixbuf2.0-0 libgdk-pixbuf2.0-bin libgdk-pixbuf2.0-common libgtk2.0-0 libgtk2.0-bin 7 upgraded, 60 newly installed, 0 to remove and 146 not upgraded. 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[rtd-command-info] start-time: 2025-01-26T20:52:38.436528Z, end-time: 2025-01-26T20:52:38.501550Z, duration: 0, exit-code: 0 asdf global python 3.9.20 [rtd-command-info] start-time: 2025-01-26T20:52:40.987079Z, end-time: 2025-01-26T20:52:41.057419Z, duration: 0, exit-code: 0 asdf global nodejs 20.18.0 [rtd-command-info] start-time: 2025-01-26T20:52:44.336931Z, end-time: 2025-01-26T20:52:44.399717Z, duration: 0, exit-code: 0 asdf global ruby 3.3.5 [rtd-command-info] start-time: 2025-01-26T20:52:44.664467Z, end-time: 2025-01-26T20:52:45.555367Z, duration: 0, exit-code: 0 python -mvirtualenv $READTHEDOCS_VIRTUALENV_PATH created virtual environment CPython3.9.20.final.0-64 in 659ms creator CPython3Posix(dest=/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/envs/latest, clear=False, no_vcs_ignore=False, global=False) seeder FromAppData(download=False, pip=bundle, setuptools=bundle, wheel=bundle, via=copy, app_data_dir=/home/docs/.local/share/virtualenv) added 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importlib_metadata-8.6.1-py3-none-any.whl (26 kB) Downloading jinja2-3.1.5-py3-none-any.whl (134 kB) Downloading packaging-24.2-py3-none-any.whl (65 kB) Downloading pygments-2.19.1-py3-none-any.whl (1.2 MB) ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ 1.2/1.2 MB 484.5 MB/s eta 0:00:00 Downloading requests-2.32.3-py3-none-any.whl (64 kB) Downloading snowballstemmer-2.2.0-py2.py3-none-any.whl (93 kB) Downloading sphinxcontrib_htmlhelp-2.1.0-py3-none-any.whl (98 kB) Downloading sphinxcontrib_serializinghtml-2.0.0-py3-none-any.whl (92 kB) Downloading tomli-2.2.1-py3-none-any.whl (14 kB) Downloading sphinxcontrib_applehelp-2.0.0-py3-none-any.whl (119 kB) Downloading sphinxcontrib_devhelp-2.0.0-py3-none-any.whl (82 kB) Downloading sphinxcontrib_jsmath-1.0.1-py2.py3-none-any.whl (5.1 kB) Downloading sphinxcontrib_qthelp-2.0.0-py3-none-any.whl (88 kB) Downloading certifi-2024.12.14-py3-none-any.whl (164 kB) Downloading charset_normalizer-3.4.1-cp39-cp39-manylinux_2_17_x86_64.manylinux2014_x86_64.whl (146 kB) Downloading idna-3.10-py3-none-any.whl (70 kB) Downloading MarkupSafe-3.0.2-cp39-cp39-manylinux_2_17_x86_64.manylinux2014_x86_64.whl (20 kB) Downloading urllib3-2.3.0-py3-none-any.whl (128 kB) Downloading zipp-3.21.0-py3-none-any.whl (9.6 kB) Installing collected packages: snowballstemmer, zipp, urllib3, tomli, sphinxcontrib-serializinghtml, sphinxcontrib-qthelp, sphinxcontrib-jsmath, sphinxcontrib-htmlhelp, sphinxcontrib-devhelp, sphinxcontrib-applehelp, Pygments, packaging, MarkupSafe, imagesize, idna, docutils, charset-normalizer, certifi, babel, alabaster, requests, Jinja2, importlib-metadata, sphinx Successfully installed Jinja2-3.1.5 MarkupSafe-3.0.2 Pygments-2.19.1 alabaster-0.7.16 babel-2.16.0 certifi-2024.12.14 charset-normalizer-3.4.1 docutils-0.21.2 idna-3.10 imagesize-1.4.1 importlib-metadata-8.6.1 packaging-24.2 requests-2.32.3 snowballstemmer-2.2.0 sphinx-7.4.7 sphinxcontrib-applehelp-2.0.0 sphinxcontrib-devhelp-2.0.0 sphinxcontrib-htmlhelp-2.1.0 sphinxcontrib-jsmath-1.0.1 sphinxcontrib-qthelp-2.0.0 sphinxcontrib-serializinghtml-2.0.0 tomli-2.2.1 urllib3-2.3.0 zipp-3.21.0 [rtd-command-info] start-time: 2025-01-26T20:53:00.735025Z, end-time: 2025-01-26T20:53:05.401639Z, duration: 4, exit-code: 0 python -m pip install --exists-action=w --no-cache-dir -r docs/requirements.txt Requirement already satisfied: sphinx>=3.1.2 in /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/envs/latest/lib/python3.9/site-packages (from -r docs/requirements.txt (line 1)) (7.4.7) Collecting sphinx-rtd-theme (from -r docs/requirements.txt (line 2)) Downloading sphinx_rtd_theme-3.0.2-py2.py3-none-any.whl.metadata (4.4 kB) Collecting recommonmark (from -r docs/requirements.txt (line 3)) Downloading recommonmark-0.7.1-py2.py3-none-any.whl.metadata (463 bytes) Collecting sphinxcontrib-svg2pdfconverter (from -r docs/requirements.txt (line 4)) Downloading sphinxcontrib_svg2pdfconverter-1.2.3-py3-none-any.whl.metadata (3.3 kB) Collecting sphinx_github_changelog (from -r docs/requirements.txt (line 5)) Downloading sphinx_github_changelog-1.4.0-py3-none-any.whl.metadata (10.0 kB) Collecting mako (from -r docs/requirements.txt (line 8)) Downloading Mako-1.3.8-py3-none-any.whl.metadata (2.9 kB) Collecting mdutils (from -r docs/requirements.txt (line 9)) Downloading mdutils-1.6.0.tar.gz (22 kB) Installing build dependencies: started Installing build dependencies: finished with status 'done' Getting requirements to build wheel: started Getting requirements to build wheel: finished with status 'done' Preparing metadata (pyproject.toml): started Preparing metadata (pyproject.toml): finished with status 'done' Collecting pyyaml (from -r docs/requirements.txt (line 10)) Downloading PyYAML-6.0.2-cp39-cp39-manylinux_2_17_x86_64.manylinux2014_x86_64.whl.metadata (2.1 kB) Collecting rstcloth (from -r docs/requirements.txt (line 11)) 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/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/envs/latest/lib/python3.9/site-packages (from importlib-metadata>=6.0->sphinx>=3.1.2->-r docs/requirements.txt (line 1)) (3.21.0) Requirement already satisfied: charset-normalizer<4,>=2 in /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/envs/latest/lib/python3.9/site-packages (from requests>=2.30.0->sphinx>=3.1.2->-r docs/requirements.txt (line 1)) (3.4.1) Requirement already satisfied: idna<4,>=2.5 in /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/envs/latest/lib/python3.9/site-packages (from requests>=2.30.0->sphinx>=3.1.2->-r docs/requirements.txt (line 1)) (3.10) Requirement already satisfied: urllib3<3,>=1.21.1 in /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/envs/latest/lib/python3.9/site-packages (from requests>=2.30.0->sphinx>=3.1.2->-r docs/requirements.txt (line 1)) (2.3.0) Requirement already satisfied: certifi>=2017.4.17 in /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/envs/latest/lib/python3.9/site-packages (from requests>=2.30.0->sphinx>=3.1.2->-r docs/requirements.txt (line 1)) (2024.12.14) Downloading sphinx_rtd_theme-3.0.2-py2.py3-none-any.whl (7.7 MB) ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ 7.7/7.7 MB 146.3 MB/s eta 0:00:00 Downloading recommonmark-0.7.1-py2.py3-none-any.whl (10 kB) Downloading sphinxcontrib_svg2pdfconverter-1.2.3-py3-none-any.whl (8.2 kB) Downloading sphinx_github_changelog-1.4.0-py3-none-any.whl (8.5 kB) Downloading Mako-1.3.8-py3-none-any.whl (78 kB) Downloading PyYAML-6.0.2-cp39-cp39-manylinux_2_17_x86_64.manylinux2014_x86_64.whl (737 kB) ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ 737.4/737.4 kB 209.8 MB/s eta 0:00:00 Downloading rstcloth-0.6.0-py3-none-any.whl (9.1 kB) Downloading commonmark-0.9.1-py2.py3-none-any.whl (51 kB) Downloading sphinxcontrib_jquery-4.1-py2.py3-none-any.whl (121 kB) Downloading tabulate-0.9.0-py3-none-any.whl (35 kB) Building wheels for collected packages: mdutils Building wheel for mdutils (pyproject.toml): started Building wheel for mdutils (pyproject.toml): finished with status 'done' Created wheel for mdutils: filename=mdutils-1.6.0-py3-none-any.whl size=20786 sha256=b46a0fbbb789c1872f55c69b003059331f67581343b5ee0845ea744f88a9d27e Stored in directory: /tmp/pip-ephem-wheel-cache-grfkr6cj/wheels/8b/32/e5/97d618613bce92f44c6743997d755573b172d019b916204e48 Successfully built mdutils Installing collected packages: mdutils, commonmark, tabulate, pyyaml, mako, rstcloth, sphinxcontrib-svg2pdfconverter, sphinxcontrib-jquery, sphinx_github_changelog, recommonmark, sphinx-rtd-theme Successfully installed commonmark-0.9.1 mako-1.3.8 mdutils-1.6.0 pyyaml-6.0.2 recommonmark-0.7.1 rstcloth-0.6.0 sphinx-rtd-theme-3.0.2 sphinx_github_changelog-1.4.0 sphinxcontrib-jquery-4.1 sphinxcontrib-svg2pdfconverter-1.2.3 tabulate-0.9.0 [rtd-command-info] start-time: 2025-01-26T20:53:05.483734Z, end-time: 2025-01-26T20:53:18.998251Z, duration: 13, exit-code: 0 npm install docs/riscv-isa/riscv-isa-manual/dependencies npm warn deprecated glob@7.2.3: Glob versions prior to v9 are no longer supported npm warn deprecated inflight@1.0.6: This module is not supported, and leaks memory. Do not use it. Check out lru-cache if you want a good and tested way to coalesce async requests by a key value, which is much more comprehensive and powerful. npm warn deprecated are-we-there-yet@2.0.0: This package is no longer supported. npm warn deprecated gauge@3.0.2: This package is no longer supported. npm warn deprecated w3c-hr-time@1.0.2: Use your platform's native performance.now() and performance.timeOrigin. npm warn deprecated domexception@2.0.1: Use your platform's native DOMException instead npm warn deprecated abab@2.0.6: Use your platform's native atob() and btoa() methods instead npm warn deprecated npmlog@5.0.1: This package is no longer supported. npm warn deprecated rimraf@3.0.2: Rimraf versions prior to v4 are no longer supported added 177 packages in 13s 10 packages are looking for funding run `npm fund` for details npm notice npm notice New major version of npm available! 10.8.2 -> 11.0.0 npm notice Changelog: https://github.com/npm/cli/releases/tag/v11.0.0 npm notice To update run: npm install -g npm@11.0.0 npm notice [rtd-command-info] start-time: 2025-01-26T20:53:19.062442Z, end-time: 2025-01-26T20:54:08.030691Z, duration: 48, exit-code: 0 gem install -g docs/riscv-isa/riscv-isa-manual/dependencies/Gemfile Installing asciidoctor (2.0.23) Installing latex-decode (0.4.0) Installing rexml (3.4.0) Installing racc (1.8.1) Building native extensions. This could take a while... Installing namae (1.2.0) Installing csl (1.6.0) Installing csl-styles (1.0.1.11) Installing uri (1.0.2) Installing date (3.4.1) Building native extensions. This could take a while... Installing time (0.4.1) Installing stringio (3.1.2) Building native extensions. This could take a while... Installing open-uri (0.5.0) Using observer (0.1.2) Installing json (2.9.1) Building native extensions. This could take a while... Using forwardable (1.3.3) Installing citeproc (1.1.0) Installing citeproc-ruby (1.1.14) Installing bibtex-ruby (6.1.0) Installing asciidoctor-bibtex (0.9.0) Installing asciidoctor-diagram-batik (1.17) Installing asciidoctor-diagram-plantuml (1.2024.8) Installing asciidoctor-diagram-ditaamini (1.0.3) Installing asciidoctor-diagram (2.3.1) Installing asciidoctor-lists (1.1.2) Installing ruby-enum (1.0.0) Installing mathematical (1.6.20) Building native extensions. This could take a while... Installing asciimath (2.0.5) Installing asciidoctor-mathematical (0.3.5) Installing ttfunk (1.7.0) Installing polyglot (0.3.5) Installing treetop (1.6.14) Installing pdf-core (0.9.0) Installing prawn (2.4.0) Installing ruby-rc4 (0.1.5) Installing hashery (2.1.2) Installing Ascii85 (2.0.1) Installing afm (0.2.2) Installing pdf-reader (2.13.0) Installing prawn-templates (0.1.2) Installing prawn-table (0.2.2) Using matrix (0.4.2) Installing public_suffix (6.0.1) Installing addressable (2.8.7) Installing css_parser (1.21.0) Installing prawn-svg (0.34.2) Installing prawn-icon (3.0.0) Installing concurrent-ruby (1.3.5) Installing asciidoctor-pdf (2.3.19) Installing ffi (1.17.1) Installing rb-inotify (0.11.1) Installing rb-fsevent (0.11.2) Installing sass-listen (4.0.0) Installing sass (3.7.4) Ruby Sass has reached end-of-life and should no longer be used. * If you use Sass as a command-line tool, we recommend using Dart Sass, the new primary implementation: https://sass-lang.com/install * If you use Sass as a plug-in for a Ruby web framework, we recommend using the sassc gem: https://github.com/sass/sassc-ruby#readme * For more details, please refer to the Sass blog: https://sass-lang.com/blog/posts/7828841 Installing mime-types-data (3.2025.0107) Installing logger (1.6.5) Installing mime-types (3.6.0) Installing rubyzip (2.3.2) RubyZip 3.0 is coming! ********************** The public API of some Rubyzip classes has been modernized to use named parameters for optional arguments. Please check your usage of the following classes: * `Zip::File` * `Zip::Entry` * `Zip::InputStream` * `Zip::OutputStream` Please ensure that your Gemfiles and .gemspecs are suitably restrictive to avoid an unexpected breakage when 3.0 is released (e.g. ~> 2.3.0). See https://github.com/rubyzip/rubyzip for details. The Changelog also lists other enhancements and bugfixes that have been implemented since version 2.3.0. Installing nokogiri (1.18.2) Installing gepub (1.0.15) Installing asciidoctor-epub3 (2.1.3) Installing coderay (1.1.3) Installing pygments.rb (3.0.0) Installing rghost (0.9.9) Installing rouge (4.5.1) Installing ruby_dev (0.1.0) [rtd-command-info] start-time: 2025-01-26T20:54:08.215500Z, end-time: 2025-01-26T20:56:19.510943Z, duration: 131, exit-code: 0 PATH=$PWD/node_modules/.bin:$PATH make -C docs prepare make: Entering directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs' make -C 04_cv32a65x/riscv priv-html unpriv-html make[1]: Entering directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/riscv' mkdir -p build/riscv-isa-manual cp -r ../../riscv-isa//riscv-isa-manual/* build/riscv-isa-manual cp -r ../../riscv-isa//src build/riscv-isa-manual cp ../../riscv-isa//../common/*.adoc build/riscv-isa-manual/src cd ../.. && python3 scripts/spec_builder.py --target cv32a65x --gen-config /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/riscv/build/riscv-isa-manual/src/config.adoc Input file ../core/include/config_pkg.sv File /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/riscv/build/riscv-isa-manual/src/config.adoc written cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-privileged.html make[2]: Entering directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/riscv/build/riscv-isa-manual' rm -rf build/riscv-privileged.html.workdir && mkdir -p build/riscv-privileged.html.workdir && ln -sfn ../../src ../../docs-resources build/riscv-privileged.html.workdir/ cd build/riscv-privileged.html.workdir && LANG=C.utf8 asciidoctor --trace -a compress -a mathematical-format=svg -a pdf-fontsdir=docs-resources/fonts -a pdf-theme=docs-resources/themes/riscv-pdf.yml -D build --failure-level=ERROR --require=asciidoctor-bibtex --require=asciidoctor-diagram --require=asciidoctor-lists --require=asciidoctor-mathematical src/riscv-privileged.adoc mv build/riscv-privileged.html.workdir/build/riscv-privileged.html build/riscv-privileged.html && rm -rf build/riscv-privileged.html.workdir make[2]: Leaving directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/riscv/build/riscv-isa-manual' cp ./build/riscv-isa-manual/build/riscv-privileged.html priv-isa-cv32a65x.html cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-unprivileged.html make[2]: Entering directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/riscv/build/riscv-isa-manual' rm -rf build/riscv-unprivileged.html.workdir && mkdir -p build/riscv-unprivileged.html.workdir && ln -sfn ../../src ../../docs-resources build/riscv-unprivileged.html.workdir/ cd build/riscv-unprivileged.html.workdir && LANG=C.utf8 asciidoctor --trace -a compress -a mathematical-format=svg -a pdf-fontsdir=docs-resources/fonts -a pdf-theme=docs-resources/themes/riscv-pdf.yml -D build --failure-level=ERROR --require=asciidoctor-bibtex --require=asciidoctor-diagram --require=asciidoctor-lists --require=asciidoctor-mathematical src/riscv-unprivileged.adoc mv build/riscv-unprivileged.html.workdir/build/riscv-unprivileged.html build/riscv-unprivileged.html && rm -rf build/riscv-unprivileged.html.workdir make[2]: Leaving directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/riscv/build/riscv-isa-manual' cp ./build/riscv-isa-manual/build/riscv-unprivileged.html unpriv-isa-cv32a65x.html make[1]: Leaving directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/riscv' make -C 04_cv32a65x/design design-html make[1]: Entering directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design' mkdir -p build cp -r ../../design//design-manual/* build cp -r ../../design//../riscv-isa/riscv-isa-manual/docs-resources build cp ../../design//../common/*.adoc build/source cp -rf source/* build/source cd ../../../config/gen_from_riscv_config && python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -i templates/isa_template.yaml -m updaters/cv32a65x/isa_updater.yaml -t cv32a65x -f adoc Extensions: ['I', 'M', 'C', 'Zicsr', 'Zcb', 'Zba', 'Zbb', 'Zbc', 'Zbs'] writing file ./cv32a65x/isa/isa.adoc cd ../../../config/gen_from_riscv_config && python3 scripts/riscv_config_gen.py -s ../riscv-config/cv32a65x/generated/isa_gen.yaml -c ../riscv-config/cv32a65x/generated/custom_gen.yaml -m updaters/cv32a65x/csr_updater.yaml -t cv32a65x -f adoc {'ISA': 'RV32IMCZicsr_Zcb_Zba_Zbb_Zbc_Zbs', 'User_Spec_Version': '2.3', 'supported_xlen': [32], 'physical_addr_sz': 32, 'pmp_granularity': 8, 'misa': {'reset-val': 1073746182, 'rv32': {'accessible': True, 'mxl': {'implemented': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['mxl[1:0] in [0x1]'], 'wr_illegal': ['unchanged']}}, 'description': 'Encodes the native base integer ISA width.', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 30}, 'extensions': {'implemented': True, 'type': {'ro_constant': 4358}, 'description': 'Encodes the presence of the standard extensions, with a single bit per letter of the alphabet.', 'shadow': None, 'shadow_type': 'rw', 'msb': 25, 'lsb': 0}, 'fields': ['extensions', 'mxl', [[26, 29]]]}, 'description': 'misa is a read-write register reporting the ISA supported by the hart.', 'address': 769, 'priv_mode': 'M', 'rv64': {'accessible': False}}, 'mvendorid': {'reset-val': 1538, 'rv32': {'accessible': True, 'type': {'ro_constant': 1538}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'description': '32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core.', 'address': 3857, 'priv_mode': 'M'}, 'mtvec': {'reset-val': 2147549184, 'rv32': {'accessible': True, 'base': {'implemented': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['base[29:0] in [0x00000000:0x3FFFFFFF]'], 'wr_illegal': ['Unchanged']}}, 'description': 'Vector base address.', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 2}, 'mode': {'implemented': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['mode[1:0] in [0x0]'], 'wr_illegal': ['Unchanged']}}, 'description': 'Vector mode.', 'shadow': None, 'shadow_type': 'rw', 'msb': 1, 'lsb': 0}, 'fields': ['mode', 'base']}, 'description': 'MXLEN-bit read/write register that holds trap vector configuration.', 'address': 773, 'priv_mode': 'M', 'rv64': {'accessible': False}}, 'sstatus': {'reset-val': 0, 'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The sstatus register keeps track of the processor’s current operating state.', 'address': 256, 'priv_mode': 'S'}, 'vsstatus': {'reset-val': 0, 'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The vsstatus register keeps track of the processor’s current operating state.', 'address': 512, 'priv_mode': 'S'}, 'mstatus': {'reset-val': 6144, 'rv32': {'accessible': True, 'uie': {'implemented': False, 'description': 'Stores the state of the user mode interrupts.', 'shadow': None, 'shadow_type': 'rw', 'msb': 0, 'lsb': 0}, 'sie': {'implemented': False, 'description': 'Stores the state of the supervisor mode interrupts.', 'shadow': None, 'shadow_type': 'rw', 'msb': 1, 'lsb': 1}, 'mie': {'implemented': True, 'description': 'Stores the state of the machine mode interrupts.', 'shadow': None, 'shadow_type': 'rw', 'msb': 3, 'lsb': 3, 'type': {'wlrl': ['0:1']}}, 'upie': {'implemented': False, 'description': 'Stores the state of the user mode interrupts prior to the trap.', 'shadow': None, 'shadow_type': 'rw', 'msb': 4, 'lsb': 4}, 'spie': {'implemented': False, 'description': 'Stores the state of the supervisor mode interrupts prior to the trap.', 'shadow': None, 'shadow_type': 'rw', 'msb': 5, 'lsb': 5}, 'ube': {'implemented': False, 'description': 'control the endianness of memory accesses other than instruction fetches for user mode', 'shadow': None, 'shadow_type': 'rw', 'msb': 6, 'lsb': 6}, 'mpie': {'implemented': True, 'description': 'Stores the state of the machine mode interrupts prior to the trap.', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 7, 'type': {'wlrl': ['0:1']}}, 'spp': {'implemented': False, 'description': 'Stores the previous priority mode for supervisor.', 'shadow': None, 'shadow_type': 'rw', 'msb': 8, 'lsb': 8}, 'mpp': {'implemented': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['mpp[1:0] in [0x3]'], 'wr_illegal': ['Unchanged']}}, 'description': 'Stores the previous priority mode for machine.', 'shadow': None, 'shadow_type': 'rw', 'msb': 12, 'lsb': 11}, 'fs': {'implemented': False, 'description': 'Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers.', 'shadow': None, 'shadow_type': 'rw', 'msb': 14, 'lsb': 13}, 'xs': {'implemented': False, 'description': 'Encodes the status of additional user-mode extensions and associated state.', 'shadow': None, 'shadow_type': 'rw', 'msb': 16, 'lsb': 15}, 'mprv': {'implemented': False, 'description': 'Modifies the privilege level at which loads and stores execute in all privilege modes.', 'shadow': None, 'shadow_type': 'rw', 'msb': 17, 'lsb': 17}, 'sum': {'implemented': False, 'description': 'Modifies the privilege with which S-mode loads and stores access virtual memory.', 'shadow': None, 'shadow_type': 'rw', 'msb': 18, 'lsb': 18}, 'mxr': {'implemented': False, 'description': 'Modifies the privilege with which loads access virtual memory.', 'shadow': None, 'shadow_type': 'rw', 'msb': 19, 'lsb': 19}, 'tvm': {'implemented': False, 'description': 'Supports intercepting supervisor virtual-memory management operations.', 'shadow': None, 'shadow_type': 'rw', 'msb': 20, 'lsb': 20}, 'tw': {'implemented': False, 'description': 'Supports intercepting the WFI instruction.', 'shadow': None, 'shadow_type': 'rw', 'msb': 21, 'lsb': 21}, 'tsr': {'implemented': False, 'description': 'Supports intercepting the supervisor exception return instruction.', 'shadow': None, 'shadow_type': 'rw', 'msb': 22, 'lsb': 22}, 'sd': {'implemented': False, 'description': 'Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state.', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 31}, 'fields': ['uie', 'sie', 'mie', 'upie', 'spie', 'ube', 'mpie', 'spp', 'mpp', 'fs', 'xs', 'mprv', 'sum', 'mxr', 'tvm', 'tw', 'tsr', 'spelp', 'sd', [[2], [9, 10], [24, 30]]], 'spelp': {'implemented': False, 'description': 'Supervisor mode previous expected-landing-pad (ELP) state.', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 23}}, 'rv64': {'accessible': False}, 'description': "The mstatus register keeps track of and controls the hart's current operating state.", 'address': 768, 'priv_mode': 'M'}, 'mip': {'reset-val': 0, 'rv32': {'accessible': True, 'usip': {'implemented': False, 'description': 'User Software Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 0, 'lsb': 0}, 'ssip': {'implemented': False, 'description': 'Supervisor Software Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 1, 'lsb': 1}, 'msip': {'implemented': False, 'description': 'Machine Software Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 3, 'lsb': 3}, 'utip': {'implemented': False, 'description': 'User Timer Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 4, 'lsb': 4}, 'stip': {'implemented': False, 'description': 'Supervisor Timer Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 5, 'lsb': 5}, 'mtip': {'implemented': True, 'description': 'Machine Timer Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 7, 'type': {'ro_variable': True}}, 'ueip': {'implemented': False, 'description': 'User External Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 8, 'lsb': 8}, 'seip': {'implemented': False, 'description': 'Supervisor External Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 9, 'lsb': 9}, 'meip': {'implemented': True, 'description': 'Machine External Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 11, 'lsb': 11, 'type': {'ro_variable': True}}, 'fields': ['usip', 'ssip', 'vssip', 'msip', 'utip', 'stip', 'vstip', 'mtip', 'ueip', 'seip', 'vseip', 'meip', 'sgeip', [[13, 31]]], 'vssip': {'implemented': False, 'description': 'VS-level Software Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 2, 'lsb': 2}, 'vstip': {'implemented': False, 'description': 'VS-level Timer Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 6, 'lsb': 6}, 'vseip': {'implemented': False, 'description': 'VS-level External Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 10, 'lsb': 10}, 'sgeip': {'implemented': False, 'description': 'HS-level External Interrupt Pending.', 'shadow': None, 'shadow_type': 'rw', 'msb': 12, 'lsb': 12}}, 'rv64': {'accessible': False}, 'description': 'The mip register is an MXLEN-bit read/write register containing information on pending interrupts.', 'address': 836, 'priv_mode': 'M'}, 'hip': {'reset-val': 0, 'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The hip register is an HXLEN-bit read/write register containing information on pending interrupts.', 'address': 1604, 'priv_mode': 'H'}, 'mie': {'reset-val': 0, 'rv32': {'accessible': True, 'usie': {'implemented': False, 'description': 'User Software Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 0, 'lsb': 0}, 'ssie': {'implemented': False, 'description': 'Supervisor Software Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 1, 'lsb': 1}, 'msie': {'implemented': False, 'description': 'Machine Software Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 3, 'lsb': 3}, 'utie': {'implemented': False, 'description': 'User Timer Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 4, 'lsb': 4}, 'stie': {'implemented': False, 'description': 'Supervisor Timer Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 5, 'lsb': 5}, 'mtie': {'implemented': True, 'description': 'Machine Timer Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 7, 'type': {'wlrl': ['0:1']}}, 'ueie': {'implemented': False, 'description': 'User External Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 8, 'lsb': 8}, 'seie': {'implemented': False, 'description': 'Supervisor External Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 9, 'lsb': 9}, 'meie': {'implemented': True, 'description': 'Machine External Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 11, 'lsb': 11, 'type': {'wlrl': ['0:1']}}, 'fields': ['usie', 'ssie', 'vssie', 'msie', 'utie', 'stie', 'vstie', 'mtie', 'ueie', 'seie', 'vseie', 'meie', 'sgeie', [[13, 31]]], 'vssie': {'implemented': False, 'description': 'VS-level Software Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 2, 'lsb': 2}, 'vstie': {'implemented': False, 'description': 'VS-level Timer Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 6, 'lsb': 6}, 'vseie': {'implemented': False, 'description': 'VS-level External Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 10, 'lsb': 10}, 'sgeie': {'implemented': False, 'description': 'HS-level External Interrupt enable.', 'shadow': None, 'shadow_type': 'rw', 'msb': 12, 'lsb': 12}}, 'rv64': {'accessible': False}, 'description': 'The mie register is an MXLEN-bit read/write register containing interrupt enable bits.', 'address': 772, 'priv_mode': 'M'}, 'hie': {'reset-val': 0, 'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The hie register is an HSXLEN-bit read/write register containing interrupt enable bits.', 'address': 1540, 'priv_mode': 'H'}, 'mepc': {'reset-val': 0, 'rv32': {'accessible': True, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0, 'type': {'warl': {'dependency_fields': [], 'legal': ['mepc[31:0] in [0x00000000:0xFFFFFFFF]'], 'wr_illegal': ['unchanged']}}}, 'rv64': {'accessible': False}, 'description': 'The mepc is a warl register that must be able to hold all valid physical and virtual addresses.', 'address': 833, 'priv_mode': 'M'}, 'mtval': {'reset-val': 0, 'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'description': 'The mtval is a warl register that holds the address of the instruction which caused the exception.', 'address': 835, 'priv_mode': 'M'}, 'mcause': {'reset-val': 0, 'rv32': {'accessible': True, 'interrupt': {'implemented': True, 'description': 'Indicates whether the trap was due to an interrupt.', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 31, 'type': {'wlrl': ['0x0:0x1']}}, 'exception_code': {'implemented': True, 'description': 'Encodes the exception code.', 'shadow': None, 'shadow_type': 'rw', 'msb': 30, 'lsb': 0, 'type': {'wlrl': ['0:15']}}, 'fields': ['exception_code', 'interrupt']}, 'rv64': {'accessible': False}, 'description': 'The mcause register stores the information regarding the trap.', 'address': 834, 'priv_mode': 'M'}, 'marchid': {'rv32': {'accessible': True, 'type': {'ro_constant': 3}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 3, 'description': 'MXLEN-bit read-only register encoding the base microarchitecture of the hart.', 'address': 3858, 'priv_mode': 'M'}, 'mhartid': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'MXLEN-bit read-only register containing the integer ID of the hardware thread running the code.', 'address': 3860, 'priv_mode': 'M'}, 'mconfigptr': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'MXLEN-bit read-only register that holds the physical address of a configuration data structure.', 'address': 3861, 'priv_mode': 'M'}, 'mscratch': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['mscratch[31:0] in [0x00000000:0xFFFFFFFF]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.', 'address': 832, 'priv_mode': 'M'}, 'mhpmcounter3': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter3 is a 64-bit counter. Returns lower 32 bits in RV32I mode.', 'address': 2819, 'priv_mode': 'M'}, 'mhpmcounter4': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter4 is a 64-bit counter. Returns lower 42 bits in RV42I mode.', 'address': 2820, 'priv_mode': 'M'}, 'mhpmcounter5': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter5 is a 64-bit counter. Returns lower 52 bits in RV52I mode.', 'address': 2821, 'priv_mode': 'M'}, 'mhpmcounter6': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter6 is a 64-bit counter. Returns lower 62 bits in RV62I mode.', 'address': 2822, 'priv_mode': 'M'}, 'mhpmcounter7': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter7 is a 64-bit counter. Returns lower 72 bits in RV72I mode.', 'address': 2823, 'priv_mode': 'M'}, 'mhpmcounter8': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter8 is a 64-bit counter. Returns lower 82 bits in RV82I mode.', 'address': 2824, 'priv_mode': 'M'}, 'mhpmcounter9': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter9 is a 64-bit counter. Returns lower 32 bits in RV32I mode.', 'address': 2825, 'priv_mode': 'M'}, 'mhpmcounter10': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter10 is a 64-bit counter. Returns lower 102 bits in RV102I mode.', 'address': 2826, 'priv_mode': 'M'}, 'mhpmcounter11': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter11 is a 64-bit counter. Returns lower 112 bits in RV112I mode.', 'address': 2827, 'priv_mode': 'M'}, 'mhpmcounter12': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter12 is a 64-bit counter. Returns lower 122 bits in RV122I mode.', 'address': 2828, 'priv_mode': 'M'}, 'mhpmcounter13': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter13 is a 64-bit counter. Returns lower 132 bits in RV132I mode.', 'address': 2829, 'priv_mode': 'M'}, 'mhpmcounter14': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter14 is a 64-bit counter. Returns lower 142 bits in RV142I mode.', 'address': 2830, 'priv_mode': 'M'}, 'mhpmcounter15': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter15 is a 64-bit counter. Returns lower 152 bits in RV152I mode.', 'address': 2831, 'priv_mode': 'M'}, 'mhpmcounter16': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter16 is a 64-bit counter. Returns lower 162 bits in RV162I mode.', 'address': 2832, 'priv_mode': 'M'}, 'mhpmcounter17': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter17 is a 64-bit counter. Returns lower 172 bits in RV172I mode.', 'address': 2833, 'priv_mode': 'M'}, 'mhpmcounter18': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter18 is a 64-bit counter. Returns lower 182 bits in RV182I mode.', 'address': 2834, 'priv_mode': 'M'}, 'mhpmcounter19': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter19 is a 64-bit counter. Returns lower 32 bits in RV32I mode.', 'address': 2835, 'priv_mode': 'M'}, 'mhpmcounter20': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter20 is a 64-bit counter. Returns lower 202 bits in RV202I mode.', 'address': 2836, 'priv_mode': 'M'}, 'mhpmcounter21': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter21 is a 64-bit counter. Returns lower 212 bits in RV212I mode.', 'address': 2837, 'priv_mode': 'M'}, 'mhpmcounter22': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter22 is a 64-bit counter. Returns lower 222 bits in RV222I mode.', 'address': 2838, 'priv_mode': 'M'}, 'mhpmcounter23': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter23 is a 64-bit counter. Returns lower 232 bits in RV232I mode.', 'address': 2839, 'priv_mode': 'M'}, 'mhpmcounter24': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter24 is a 64-bit counter. Returns lower 242 bits in RV242I mode.', 'address': 2840, 'priv_mode': 'M'}, 'mhpmcounter25': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter25 is a 64-bit counter. Returns lower 252 bits in RV252I mode.', 'address': 2841, 'priv_mode': 'M'}, 'mhpmcounter26': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter26 is a 64-bit counter. Returns lower 262 bits in RV262I mode.', 'address': 2842, 'priv_mode': 'M'}, 'mhpmcounter27': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter27 is a 64-bit counter. Returns lower 272 bits in RV272I mode.', 'address': 2843, 'priv_mode': 'M'}, 'mhpmcounter28': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter28 is a 64-bit counter. Returns lower 282 bits in RV282I mode.', 'address': 2844, 'priv_mode': 'M'}, 'mhpmcounter29': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter29 is a 64-bit counter. Returns lower 32 bits in RV32I mode.', 'address': 2845, 'priv_mode': 'M'}, 'mhpmcounter30': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter30 is a 64-bit counter. Returns lower 302 bits in RV302I mode.', 'address': 2846, 'priv_mode': 'M'}, 'mhpmcounter31': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter31 is a 64-bit counter. Returns lower 312 bits in RV312I mode.', 'address': 2847, 'priv_mode': 'M'}, 'mhpmcounter3h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter3h returns the upper half word in RV32I systems.', 'address': 2947, 'priv_mode': 'M'}, 'mhpmcounter4h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter4h returns the upper half word in RV42I systems.', 'address': 2948, 'priv_mode': 'M'}, 'mhpmcounter5h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter5h returns the upper half word in RV52I systems.', 'address': 2949, 'priv_mode': 'M'}, 'mhpmcounter6h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter6h returns the upper half word in RV62I systems.', 'address': 2950, 'priv_mode': 'M'}, 'mhpmcounter7h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter7h returns the upper half word in RV72I systems.', 'address': 2951, 'priv_mode': 'M'}, 'mhpmcounter8h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter8h returns the upper half word in RV82I systems.', 'address': 2952, 'priv_mode': 'M'}, 'mhpmcounter9h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter9h returns the upper half word in RV32I systems.', 'address': 2953, 'priv_mode': 'M'}, 'mhpmcounter10h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter10h returns the upper half word in RV102I systems.', 'address': 2954, 'priv_mode': 'M'}, 'mhpmcounter11h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter11h returns the upper half word in RV112I systems.', 'address': 2955, 'priv_mode': 'M'}, 'mhpmcounter12h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter12h returns the upper half word in RV122I systems.', 'address': 2956, 'priv_mode': 'M'}, 'mhpmcounter13h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter13h returns the upper half word in RV132I systems.', 'address': 2957, 'priv_mode': 'M'}, 'mhpmcounter14h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter14h returns the upper half word in RV142I systems.', 'address': 2958, 'priv_mode': 'M'}, 'mhpmcounter15h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter15h returns the upper half word in RV152I systems.', 'address': 2959, 'priv_mode': 'M'}, 'mhpmcounter16h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter16h returns the upper half word in RV162I systems.', 'address': 2960, 'priv_mode': 'M'}, 'mhpmcounter17h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter17h returns the upper half word in RV172I systems.', 'address': 2961, 'priv_mode': 'M'}, 'mhpmcounter18h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter18h returns the upper half word in RV182I systems.', 'address': 2962, 'priv_mode': 'M'}, 'mhpmcounter19h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter19h returns the upper half word in RV32I systems.', 'address': 2963, 'priv_mode': 'M'}, 'mhpmcounter20h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter20h returns the upper half word in RV202I systems.', 'address': 2964, 'priv_mode': 'M'}, 'mhpmcounter21h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter21h returns the upper half word in RV212I systems.', 'address': 2965, 'priv_mode': 'M'}, 'mhpmcounter22h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter22h returns the upper half word in RV222I systems.', 'address': 2966, 'priv_mode': 'M'}, 'mhpmcounter23h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter23h returns the upper half word in RV232I systems.', 'address': 2967, 'priv_mode': 'M'}, 'mhpmcounter24h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter24h returns the upper half word in RV242I systems.', 'address': 2968, 'priv_mode': 'M'}, 'mhpmcounter25h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter25h returns the upper half word in RV252I systems.', 'address': 2969, 'priv_mode': 'M'}, 'mhpmcounter26h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter26h returns the upper half word in RV262I systems.', 'address': 2970, 'priv_mode': 'M'}, 'mhpmcounter27h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter27h returns the upper half word in RV272I systems.', 'address': 2971, 'priv_mode': 'M'}, 'mhpmcounter28h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter28h returns the upper half word in RV282I systems.', 'address': 2972, 'priv_mode': 'M'}, 'mhpmcounter29h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter29h returns the upper half word in RV32I systems.', 'address': 2973, 'priv_mode': 'M'}, 'mhpmcounter30h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter30h returns the upper half word in RV302I systems.', 'address': 2974, 'priv_mode': 'M'}, 'mhpmcounter31h': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmcounter31h returns the upper half word in RV312I systems.', 'address': 2975, 'priv_mode': 'M'}, 'mcountinhibit': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment.', 'address': 800, 'priv_mode': 'M'}, 'mhpmevent3': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent3 is a MXLEN-bit event register which controls mhpmcounter3.', 'address': 803, 'priv_mode': 'M'}, 'mhpmevent4': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent4 is a MXLEN-bit event register which controls mhpmcounter4.', 'address': 804, 'priv_mode': 'M'}, 'mhpmevent5': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent5 is a MXLEN-bit event register which controls mhpmcounter5.', 'address': 805, 'priv_mode': 'M'}, 'mhpmevent6': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent6 is a MXLEN-bit event register which controls mhpmcounter6.', 'address': 806, 'priv_mode': 'M'}, 'mhpmevent7': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent7 is a MXLEN-bit event register which controls mhpmcounter7.', 'address': 807, 'priv_mode': 'M'}, 'mhpmevent8': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent8 is a MXLEN-bit event register which controls mhpmcounter8.', 'address': 808, 'priv_mode': 'M'}, 'mhpmevent9': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent9 is a MXLEN-bit event register which controls mhpmcounter9.', 'address': 809, 'priv_mode': 'M'}, 'mhpmevent10': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent10 is a MXLEN-bit event register which controls mhpmcounter10.', 'address': 810, 'priv_mode': 'M'}, 'mhpmevent11': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent11 is a MXLEN-bit event register which controls mhpmcounter11.', 'address': 811, 'priv_mode': 'M'}, 'mhpmevent12': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent12 is a MXLEN-bit event register which controls mhpmcounter12.', 'address': 812, 'priv_mode': 'M'}, 'mhpmevent13': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent13 is a MXLEN-bit event register which controls mhpmcounter13.', 'address': 813, 'priv_mode': 'M'}, 'mhpmevent14': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent14 is a MXLEN-bit event register which controls mhpmcounter14.', 'address': 814, 'priv_mode': 'M'}, 'mhpmevent15': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent15 is a MXLEN-bit event register which controls mhpmcounter15.', 'address': 815, 'priv_mode': 'M'}, 'mhpmevent16': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent16 is a MXLEN-bit event register which controls mhpmcounter16.', 'address': 816, 'priv_mode': 'M'}, 'mhpmevent17': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent17 is a MXLEN-bit event register which controls mhpmcounter17.', 'address': 817, 'priv_mode': 'M'}, 'mhpmevent18': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent18 is a MXLEN-bit event register which controls mhpmcounter18.', 'address': 818, 'priv_mode': 'M'}, 'mhpmevent19': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent19 is a MXLEN-bit event register which controls mhpmcounter19.', 'address': 819, 'priv_mode': 'M'}, 'mhpmevent20': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent20 is a MXLEN-bit event register which controls mhpmcounter20.', 'address': 820, 'priv_mode': 'M'}, 'mhpmevent21': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent21 is a MXLEN-bit event register which controls mhpmcounter21.', 'address': 821, 'priv_mode': 'M'}, 'mhpmevent22': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent22 is a MXLEN-bit event register which controls mhpmcounter22.', 'address': 822, 'priv_mode': 'M'}, 'mhpmevent23': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent23 is a MXLEN-bit event register which controls mhpmcounter23.', 'address': 823, 'priv_mode': 'M'}, 'mhpmevent24': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent24 is a MXLEN-bit event register which controls mhpmcounter24.', 'address': 824, 'priv_mode': 'M'}, 'mhpmevent25': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent25 is a MXLEN-bit event register which controls mhpmcounter25.', 'address': 825, 'priv_mode': 'M'}, 'mhpmevent26': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent26 is a MXLEN-bit event register which controls mhpmcounter26.', 'address': 826, 'priv_mode': 'M'}, 'mhpmevent27': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent27 is a MXLEN-bit event register which controls mhpmcounter27.', 'address': 827, 'priv_mode': 'M'}, 'mhpmevent28': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent28 is a MXLEN-bit event register which controls mhpmcounter28.', 'address': 828, 'priv_mode': 'M'}, 'mhpmevent29': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent29 is a MXLEN-bit event register which controls mhpmcounter29.', 'address': 829, 'priv_mode': 'M'}, 'mhpmevent30': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent30 is a MXLEN-bit event register which controls mhpmcounter30.', 'address': 830, 'priv_mode': 'M'}, 'mhpmevent31': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mhpmevent31 is a MXLEN-bit event register which controls mhpmcounter31.', 'address': 831, 'priv_mode': 'M'}, 'mimpid': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Provides a unique encoding of the version of the processor implementation.', 'address': 3859, 'priv_mode': 'M'}, 'mcounteren': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'The mcounteren is a 32-bit register that controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode.', 'address': 774, 'priv_mode': 'M'}, 'pmpcfg0': {'rv32': {'accessible': True, 'pmp0cfg': {'implemented': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmp0cfg[7:0] bitmask [0x8f, 0x0]'], 'wr_illegal': ['unchanged']}}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp1cfg': {'implemented': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmp1cfg[7:0] bitmask [0x8f, 0x0]'], 'wr_illegal': ['unchanged']}}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp2cfg': {'implemented': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmp2cfg[7:0] bitmask [0x8f, 0x0]'], 'wr_illegal': ['unchanged']}}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp3cfg': {'implemented': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmp3cfg[7:0] bitmask [0x8f, 0x0]'], 'wr_illegal': ['unchanged']}}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp0cfg', 'pmp1cfg', 'pmp2cfg', 'pmp3cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 928, 'priv_mode': 'M'}, 'pmpcfg1': {'rv32': {'accessible': True, 'pmp4cfg': {'implemented': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmp4cfg[7:0] bitmask [0x8f, 0x0]'], 'wr_illegal': ['unchanged']}}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp5cfg': {'implemented': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmp5cfg[7:0] bitmask [0x8f, 0x0]'], 'wr_illegal': ['unchanged']}}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp6cfg': {'implemented': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmp6cfg[7:0] bitmask [0x8f, 0x0]'], 'wr_illegal': ['unchanged']}}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp7cfg': {'implemented': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmp7cfg[7:0] bitmask [0x8f, 0x0]'], 'wr_illegal': ['unchanged']}}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp4cfg', 'pmp5cfg', 'pmp6cfg', 'pmp7cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 929, 'priv_mode': 'M'}, 'pmpcfg2': {'rv32': {'accessible': True, 'pmp8cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp9cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp10cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp11cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp8cfg', 'pmp9cfg', 'pmp10cfg', 'pmp11cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 930, 'priv_mode': 'M'}, 'pmpcfg3': {'rv32': {'accessible': True, 'pmp12cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp13cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp14cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp15cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp12cfg', 'pmp13cfg', 'pmp14cfg', 'pmp15cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 931, 'priv_mode': 'M'}, 'pmpcfg4': {'rv32': {'accessible': True, 'pmp16cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp17cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp18cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp19cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp16cfg', 'pmp17cfg', 'pmp18cfg', 'pmp19cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 932, 'priv_mode': 'M'}, 'pmpcfg5': {'rv32': {'accessible': True, 'pmp20cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp21cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp22cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp23cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp20cfg', 'pmp21cfg', 'pmp22cfg', 'pmp23cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 933, 'priv_mode': 'M'}, 'pmpcfg6': {'rv32': {'accessible': True, 'pmp24cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp25cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp26cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp27cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp24cfg', 'pmp25cfg', 'pmp26cfg', 'pmp27cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 934, 'priv_mode': 'M'}, 'pmpcfg7': {'rv32': {'accessible': True, 'pmp28cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp29cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp30cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp31cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp28cfg', 'pmp29cfg', 'pmp30cfg', 'pmp31cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 935, 'priv_mode': 'M'}, 'pmpcfg8': {'rv32': {'accessible': True, 'pmp32cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp33cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp34cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp35cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp32cfg', 'pmp33cfg', 'pmp34cfg', 'pmp35cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 936, 'priv_mode': 'M'}, 'pmpcfg9': {'rv32': {'accessible': True, 'pmp36cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp37cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp38cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp39cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp36cfg', 'pmp37cfg', 'pmp38cfg', 'pmp39cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 937, 'priv_mode': 'M'}, 'pmpcfg10': {'rv32': {'accessible': True, 'pmp40cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp41cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp42cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp43cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp40cfg', 'pmp41cfg', 'pmp42cfg', 'pmp43cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 938, 'priv_mode': 'M'}, 'pmpcfg11': {'rv32': {'accessible': True, 'pmp44cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp45cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp46cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp47cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp44cfg', 'pmp45cfg', 'pmp46cfg', 'pmp47cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 939, 'priv_mode': 'M'}, 'pmpcfg12': {'rv32': {'accessible': True, 'pmp48cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp49cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp50cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp51cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp48cfg', 'pmp49cfg', 'pmp50cfg', 'pmp51cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 940, 'priv_mode': 'M'}, 'pmpcfg13': {'rv32': {'accessible': True, 'pmp52cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp53cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp54cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp55cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp52cfg', 'pmp53cfg', 'pmp54cfg', 'pmp55cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 941, 'priv_mode': 'M'}, 'pmpcfg14': {'rv32': {'accessible': True, 'pmp56cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp57cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp58cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp59cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp56cfg', 'pmp57cfg', 'pmp58cfg', 'pmp59cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 942, 'priv_mode': 'M'}, 'pmpcfg15': {'rv32': {'accessible': True, 'pmp60cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 0}, 'pmp61cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 15, 'lsb': 8}, 'pmp62cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 23, 'lsb': 16}, 'pmp63cfg': {'implemented': True, 'type': {'ro_constant': 0}, 'description': 'pmp configuration bits', 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 24}, 'fields': ['pmp60cfg', 'pmp61cfg', 'pmp62cfg', 'pmp63cfg']}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'PMP configuration register', 'address': 943, 'priv_mode': 'M'}, 'mcycle': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['mcycle[31:0] in [0x00000000:0xFFFFFFFF]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Counts the number of clock cycles executed from an arbitrary point in time.', 'address': 2816, 'priv_mode': 'M'}, 'minstret': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['minstret[31:0] in [0x00000000:0xFFFFFFFF]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Counts the number of instructions completed from an arbitrary point in time.', 'address': 2818, 'priv_mode': 'M'}, 'mcycleh': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['mcycleh[31:0] in [0x00000000:0xFFFFFFFF]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'upper 32 bits of mcycle', 'address': 2944, 'priv_mode': 'M'}, 'minstreth': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['minstreth[31:0] in [0x00000000:0xFFFFFFFF]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Upper 32 bits of minstret.', 'address': 2946, 'priv_mode': 'M'}, 'pmpaddr0': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmpaddr0[31:0] bitmask [0xFFFFFFFE, 0x00000000]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 944, 'priv_mode': 'M'}, 'pmpaddr1': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmpaddr1[31:0] bitmask [0xFFFFFFFE, 0x00000000]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 945, 'priv_mode': 'M'}, 'pmpaddr2': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmpaddr2[31:0] bitmask [0xFFFFFFFE, 0x00000000]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 946, 'priv_mode': 'M'}, 'pmpaddr3': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmpaddr3[31:0] bitmask [0xFFFFFFFE, 0x00000000]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 947, 'priv_mode': 'M'}, 'pmpaddr4': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmpaddr4[31:0] bitmask [0xFFFFFFFE, 0x00000000]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 948, 'priv_mode': 'M'}, 'pmpaddr5': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmpaddr5[31:0] bitmask [0xFFFFFFFE, 0x00000000]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 949, 'priv_mode': 'M'}, 'pmpaddr6': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmpaddr6[31:0] bitmask [0xFFFFFFFE, 0x00000000]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 950, 'priv_mode': 'M'}, 'pmpaddr7': {'rv32': {'accessible': True, 'type': {'warl': {'dependency_fields': [], 'legal': ['pmpaddr7[31:0] bitmask [0xFFFFFFFE, 0x00000000]'], 'wr_illegal': ['unchanged']}}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 951, 'priv_mode': 'M'}, 'pmpaddr8': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 952, 'priv_mode': 'M'}, 'pmpaddr9': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 953, 'priv_mode': 'M'}, 'pmpaddr10': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 954, 'priv_mode': 'M'}, 'pmpaddr11': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 955, 'priv_mode': 'M'}, 'pmpaddr12': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 956, 'priv_mode': 'M'}, 'pmpaddr13': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 957, 'priv_mode': 'M'}, 'pmpaddr14': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 958, 'priv_mode': 'M'}, 'pmpaddr15': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 959, 'priv_mode': 'M'}, 'pmpaddr16': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 960, 'priv_mode': 'M'}, 'pmpaddr17': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 961, 'priv_mode': 'M'}, 'pmpaddr18': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 962, 'priv_mode': 'M'}, 'pmpaddr19': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 963, 'priv_mode': 'M'}, 'pmpaddr20': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 964, 'priv_mode': 'M'}, 'pmpaddr21': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 965, 'priv_mode': 'M'}, 'pmpaddr22': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 966, 'priv_mode': 'M'}, 'pmpaddr23': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 967, 'priv_mode': 'M'}, 'pmpaddr24': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 968, 'priv_mode': 'M'}, 'pmpaddr25': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 969, 'priv_mode': 'M'}, 'pmpaddr26': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 970, 'priv_mode': 'M'}, 'pmpaddr27': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 971, 'priv_mode': 'M'}, 'pmpaddr28': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 972, 'priv_mode': 'M'}, 'pmpaddr29': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 973, 'priv_mode': 'M'}, 'pmpaddr30': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 974, 'priv_mode': 'M'}, 'pmpaddr31': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 975, 'priv_mode': 'M'}, 'pmpaddr32': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 976, 'priv_mode': 'M'}, 'pmpaddr33': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 977, 'priv_mode': 'M'}, 'pmpaddr34': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 978, 'priv_mode': 'M'}, 'pmpaddr35': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 979, 'priv_mode': 'M'}, 'pmpaddr36': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 980, 'priv_mode': 'M'}, 'pmpaddr37': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 981, 'priv_mode': 'M'}, 'pmpaddr38': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 982, 'priv_mode': 'M'}, 'pmpaddr39': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 983, 'priv_mode': 'M'}, 'pmpaddr40': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 984, 'priv_mode': 'M'}, 'pmpaddr41': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 985, 'priv_mode': 'M'}, 'pmpaddr42': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 986, 'priv_mode': 'M'}, 'pmpaddr43': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 987, 'priv_mode': 'M'}, 'pmpaddr44': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 988, 'priv_mode': 'M'}, 'pmpaddr45': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 989, 'priv_mode': 'M'}, 'pmpaddr46': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 990, 'priv_mode': 'M'}, 'pmpaddr47': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 991, 'priv_mode': 'M'}, 'pmpaddr48': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 992, 'priv_mode': 'M'}, 'pmpaddr49': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 993, 'priv_mode': 'M'}, 'pmpaddr50': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 994, 'priv_mode': 'M'}, 'pmpaddr51': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 995, 'priv_mode': 'M'}, 'pmpaddr52': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 996, 'priv_mode': 'M'}, 'pmpaddr53': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 997, 'priv_mode': 'M'}, 'pmpaddr54': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 998, 'priv_mode': 'M'}, 'pmpaddr55': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 999, 'priv_mode': 'M'}, 'pmpaddr56': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 1000, 'priv_mode': 'M'}, 'pmpaddr57': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 1001, 'priv_mode': 'M'}, 'pmpaddr58': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 1002, 'priv_mode': 'M'}, 'pmpaddr59': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 1003, 'priv_mode': 'M'}, 'pmpaddr60': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 1004, 'priv_mode': 'M'}, 'pmpaddr61': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 1005, 'priv_mode': 'M'}, 'pmpaddr62': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 1006, 'priv_mode': 'M'}, 'pmpaddr63': {'rv32': {'accessible': True, 'type': {'ro_constant': 0}, 'fields': [], 'shadow': None, 'shadow_type': 'rw', 'msb': 31, 'lsb': 0}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Physical memory protection address register', 'address': 1007, 'priv_mode': 'M'}, 'fcsr': {'rv64': {'accessible': False}, 'rv32': {'accessible': False}, 'description': '32-bit register to hold Floating-Point Control and Status Register.', 'address': 3, 'priv_mode': 'U', 'reset-val': 0}, 'time': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Timer for RDTIME instruction and RTC in the processor.', 'priv_mode': 'U', 'address': 3073}, 'timeh': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'reset-val': 0, 'description': 'Upper 32-bits of the Timer for RDTIME instruction and RTC in the processor; only for rv32.', 'address': 3201, 'priv_mode': 'U'}, 'Privilege_Spec_Version': '1.10', 'hw_data_misaligned_support': False, 'custom_exceptions': None, 'custom_interrupts': None, 'pte_ad_hw_update': False, 'mtval_update': 255, 'mstatush': {'rv32': {'accessible': True, 'fields': ['sbe', 'mbe', 'gva', 'mpv', 'mpelp', [[0, 3], [8], [10, 31]]], 'mpv': {'implemented': False, 'description': 'Stores the state of the user mode interrupts.', 'shadow': None, 'shadow_type': 'rw', 'msb': 7, 'lsb': 7}, 'gva': {'implemented': False, 'description': 'Stores the state of the supervisor mode interrupts.', 'shadow': None, 'shadow_type': 'rw', 'msb': 6, 'lsb': 6}, 'mbe': {'implemented': False, 'description': 'control the endianness of memory accesses other than instruction fetches for machine mode', 'shadow': None, 'shadow_type': 'rw', 'msb': 5, 'lsb': 5}, 'sbe': {'implemented': False, 'description': 'control the endianness of memory accesses other than instruction fetches for supervisor mode', 'shadow': None, 'shadow_type': 'rw', 'msb': 4, 'lsb': 4}, 'mpelp': {'implemented': False, 'description': 'Machine mode previous expected-landing-pad (ELP) state.', 'shadow': None, 'shadow_type': 'rw', 'msb': 9, 'lsb': 9}}, 'rv64': {'accessible': False}, 'description': 'The mstatush register keeps track of and controls the hart’s current operating state.', 'address': 784, 'priv_mode': 'M', 'reset-val': 0}, 'mideleg': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'Machine Interrupt delegation Register.', 'address': 771, 'priv_mode': 'M', 'reset-val': 0}, 'medeleg': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'Machine Exception delegation Register.', 'address': 770, 'priv_mode': 'M', 'reset-val': 0}, 'sedeleg': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'sedeleg', 'address': 258, 'priv_mode': 'S', 'reset-val': 0}, 'sideleg': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'sideleg', 'priv_mode': 'S', 'address': 259, 'reset-val': 0}, 'fflags': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': '32-bit register to hold floating point accrued exceptions.', 'address': 1, 'priv_mode': 'U', 'reset-val': 0}, 'frm': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': '32-bit register to hold Floating-Point Dynamic Rounding Mode.', 'address': 2, 'priv_mode': 'U', 'reset-val': 0}, 'cycle': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'Captures the number of cycles executed from an arbitrary point in time.', 'priv_mode': 'U', 'address': 3072, 'reset-val': 0}, 'cycleh': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'Upper 32-bits of the mcycle counter; only for rv32.', 'address': 3200, 'priv_mode': 'U', 'reset-val': 0}, 'instret': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'Captures the number of instructions executed from an arbitrary point in time.', 'priv_mode': 'U', 'address': 3074, 'reset-val': 0}, 'instreth': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'Upper 32-bits of the minstret counter; only for rv32.', 'address': 3202, 'priv_mode': 'U', 'reset-val': 0}, 'hpmcounter3': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter3 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3075}, 'hpmcounter4': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter4 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3076}, 'hpmcounter5': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter5 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3077}, 'hpmcounter6': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter6 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3078}, 'hpmcounter7': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter7 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3079}, 'hpmcounter8': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter8 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3080}, 'hpmcounter9': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter9 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3081}, 'hpmcounter10': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter10 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3082}, 'hpmcounter11': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter11 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3083}, 'hpmcounter12': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter12 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3084}, 'hpmcounter13': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter13 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3085}, 'hpmcounter14': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter14 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3086}, 'hpmcounter15': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter15 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3087}, 'hpmcounter16': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter16 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3088}, 'hpmcounter17': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter17 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3089}, 'hpmcounter18': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter18 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3090}, 'hpmcounter19': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter19 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3091}, 'hpmcounter20': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter20 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3092}, 'hpmcounter21': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter21 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3093}, 'hpmcounter22': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter22 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3094}, 'hpmcounter23': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter23 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3095}, 'hpmcounter24': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter24 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3096}, 'hpmcounter25': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter25 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3097}, 'hpmcounter26': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter26 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3098}, 'hpmcounter27': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter27 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3099}, 'hpmcounter28': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter28 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3100}, 'hpmcounter29': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter29 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3101}, 'hpmcounter30': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter30 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3102}, 'hpmcounter31': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter31 is a 64-bit counter. Returns lower 32 bits in RV32UI mode.', 'address': 3103}, 'hpmcounter3h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter3h returns the upper half word in RV32I systems.', 'address': 3203}, 'hpmcounter4h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter4h returns the upper half word in RV32I systems.', 'address': 3204}, 'hpmcounter5h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter5h returns the upper half word in RV32I systems.', 'address': 3205}, 'hpmcounter6h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter6h returns the upper half word in RV32I systems.', 'address': 3206}, 'hpmcounter7h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter7h returns the upper half word in RV32I systems.', 'address': 3207}, 'hpmcounter8h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter8h returns the upper half word in RV32I systems.', 'address': 3208}, 'hpmcounter9h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter9h returns the upper half word in RV32I systems.', 'address': 3209}, 'hpmcounter10h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter10h returns the upper half word in RV32I systems.', 'address': 3210}, 'hpmcounter11h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter11h returns the upper half word in RV32I systems.', 'address': 3211}, 'hpmcounter12h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter12h returns the upper half word in RV32I systems.', 'address': 3212}, 'hpmcounter13h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter13h returns the upper half word in RV32I systems.', 'address': 3213}, 'hpmcounter14h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter14h returns the upper half word in RV32I systems.', 'address': 3214}, 'hpmcounter15h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter15h returns the upper half word in RV32I systems.', 'address': 3215}, 'hpmcounter16h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter16h returns the upper half word in RV32I systems.', 'address': 3216}, 'hpmcounter17h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter17h returns the upper half word in RV32I systems.', 'address': 3217}, 'hpmcounter18h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter18h returns the upper half word in RV32I systems.', 'address': 3218}, 'hpmcounter19h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter19h returns the upper half word in RV32I systems.', 'address': 3219}, 'hpmcounter20h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter20h returns the upper half word in RV32I systems.', 'address': 3220}, 'hpmcounter21h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter21h returns the upper half word in RV32I systems.', 'address': 3221}, 'hpmcounter22h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter22h returns the upper half word in RV32I systems.', 'address': 3222}, 'hpmcounter23h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter23h returns the upper half word in RV32I systems.', 'address': 3223}, 'hpmcounter24h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter24h returns the upper half word in RV32I systems.', 'address': 3224}, 'hpmcounter25h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter25h returns the upper half word in RV32I systems.', 'address': 3225}, 'hpmcounter26h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter26h returns the upper half word in RV32I systems.', 'address': 3226}, 'hpmcounter27h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter27h returns the upper half word in RV32I systems.', 'address': 3227}, 'hpmcounter28h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter28h returns the upper half word in RV32I systems.', 'address': 3228}, 'hpmcounter29h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter29h returns the upper half word in RV32I systems.', 'address': 3229}, 'hpmcounter30h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter30h returns the upper half word in RV32I systems.', 'address': 3230}, 'hpmcounter31h': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'priv_mode': 'U', 'reset-val': 0, 'description': 'The hpmcounter31h returns the upper half word in RV32I systems.', 'address': 3231}, 'sie': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The sie register is an SXLEN-bit read/write register containing interrupt enable bits.', 'address': 260, 'priv_mode': 'S', 'reset-val': 0}, 'sip': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The sip register is an SXLEN-bit read/write register containing interrupt pending bits.', 'address': 324, 'priv_mode': 'S', 'reset-val': 0}, 'sscratch': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The sscratch register is an MXLEN-bit read/write register dedicated for use by machine mode.', 'address': 320, 'priv_mode': 'S', 'reset-val': 0}, 'sepc': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The sepc is a warl register that must be able to hold all valid physical and virtual addresses.', 'address': 321, 'priv_mode': 'S', 'reset-val': 0}, 'stval': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The stval is a warl register that holds the address of the instruction which caused the exception.', 'address': 323, 'priv_mode': 'S', 'reset-val': 0}, 'scause': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The scause register stores the information regarding the trap.', 'address': 322, 'priv_mode': 'S', 'reset-val': 0}, 'stvec': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'SXLEN-bit read/write register that holds trap vector configuration.', 'address': 261, 'priv_mode': 'S', 'reset-val': 0}, 'satp': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'SXLEN-bit register which controls supervisor-mode address translation and protection', 'address': 384, 'priv_mode': 'S', 'reset-val': 0}, 'ustatus': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The ustatus register keeps track of the processor’s current operating state.', 'address': 0, 'priv_mode': 'U', 'reset-val': 0}, 'uie': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The uie register is an UXLEN-bit read/write register containing interrupt enable bits.', 'address': 4, 'priv_mode': 'U', 'reset-val': 0}, 'uip': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The uip register is an UXLEN-bit read/write register containing interrupt pending bits.', 'address': 68, 'priv_mode': 'U', 'reset-val': 0}, 'uscratch': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The uscratch register is an UXLEN-bit read/write register dedicated for use by machine mode.', 'address': 64, 'priv_mode': 'U', 'reset-val': 0}, 'uepc': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The uepc is a warl register that must be able to hold all valid physical and virtual addresses.', 'address': 65, 'priv_mode': 'U', 'reset-val': 0}, 'utval': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The utval is a warl register that holds the address of the instruction which caused the exception.', 'address': 67, 'priv_mode': 'U', 'reset-val': 0}, 'ucause': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The ucause register stores the information regarding the trap.', 'address': 66, 'priv_mode': 'U', 'reset-val': 0}, 'utvec': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'UXLEN-bit read/write register that holds trap vector configuration.', 'address': 5, 'priv_mode': 'U', 'reset-val': 0}, 'scounteren': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The scounteren is a 32-bit register that controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode.', 'address': 262, 'priv_mode': 'S', 'reset-val': 0}, 'hstatus': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The hstatus register keeps track of and controls the hart’s current operating state.', 'address': 1536, 'priv_mode': 'H', 'reset-val': 0}, 'hideleg': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'Hypervisor Interrupt delegation Register.', 'address': 1539, 'priv_mode': 'H', 'reset-val': 0}, 'hedeleg': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'Hypervisor Exception delegation Register.', 'address': 1538, 'priv_mode': 'H', 'reset-val': 0}, 'hvip': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The hvip register is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode.', 'address': 1605, 'priv_mode': 'H', 'reset-val': 0}, 'hgeip': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The hgeip register is an HSXLEN-bit read-only register that indicates pending guest external interrupts for this hart.', 'address': 3602, 'priv_mode': 'H', 'reset-val': 0}, 'hgeie': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The hgeie register is an HSXLEN-bit read/write register that contains enable bits for the guest external interrupts at this hart.', 'address': 1543, 'priv_mode': 'H', 'reset-val': 0}, 'htval': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The htval is a warl register that holds the address of the instruction which caused the exception.', 'address': 1603, 'priv_mode': 'H', 'reset-val': 0}, 'htinst': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The htinst is a warl register that need only be able to hold the values that the implementation may automatically write to it on a trap.', 'address': 1610, 'priv_mode': 'H', 'reset-val': 0}, 'mtval2': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'When a trap is taken into M-mode, mtval2 is written with additional exception-specific information to assist software in handling the trap.', 'address': 843, 'priv_mode': 'M', 'reset-val': 0}, 'mtinst': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The mtinst is a warl register that need only be able to hold the values that the implementation may automatically write to it on a trap.', 'address': 842, 'priv_mode': 'M', 'reset-val': 0}, 'hgatp': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'HSXLEN-bit register which controls G-stage address translation and protection', 'address': 1664, 'priv_mode': 'H', 'reset-val': 0}, 'hcounteren': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The hcounteren is a 32-bit register that controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode.', 'address': 1542, 'priv_mode': 'H', 'reset-val': 0}, 'htimedelta': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The htimedelta CSR is a read/write register that contains the delta between the value of the time CSR and the value returned in VS-mode or VU-mode.', 'priv_mode': 'H', 'address': 1541, 'reset-val': 0}, 'htimedeltah': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'Upper 32-bits of htimedelta', 'address': 1557, 'priv_mode': 'H', 'reset-val': 0}, 'vsie': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The vsie register is an VSXLEN-bit read/write register containing interrupt enable bits.', 'address': 516, 'priv_mode': 'S', 'reset-val': 0}, 'vsip': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The vsip register is an VSXLEN-bit read/write register containing interrupt pending bits.', 'address': 580, 'priv_mode': 'S', 'reset-val': 0}, 'vsscratch': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The vsscratch register is an VSXLEN-bit read/write register dedicated for use by machine mode.', 'address': 576, 'priv_mode': 'S', 'reset-val': 0}, 'vsepc': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The vsepc is a warl register that must be able to hold all valid physical and virtual addresses.', 'address': 577, 'priv_mode': 'S', 'reset-val': 0}, 'vstval': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The vstval is a warl register that holds the address of the instruction which caused the exception.', 'address': 579, 'priv_mode': 'S', 'reset-val': 0}, 'vscause': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The scause register stores the information regarding the trap.', 'address': 578, 'priv_mode': 'S', 'reset-val': 0}, 'vstvec': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'SXLEN-bit read/write register that holds trap vector configuration.', 'address': 517, 'priv_mode': 'S', 'reset-val': 0}, 'vsatp': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'VSXLEN-bit register which controls supervisor-mode address translation and protection', 'address': 640, 'priv_mode': 'S', 'reset-val': 0}, 'vxsat': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The vxsat register records the overflow saturation condition of P and V instructions.', 'address': 9, 'priv_mode': 'U', 'reset-val': 0}, 'mnscratch': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The mnscratch CSR holds an MXLEN-bit read-write register which enables the NMI trap \nhandler to save and restore the context that was interrupted.', 'address': 1856, 'priv_mode': 'M', 'reset-val': 0}, 'mnepc': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The mnepc CSR is an MXLEN-bit read-write register which on entry to the NMI trap handler holds\nthe PC of the instruction that took the interrupt.\n\nThe low bit of mnepc (mnepc[0]) is always zero. On implementations that support only\nIALIGN=32, the two low bits (mnepc[1:0]) are always zero.\n\nIf an implementation allows IALIGN to be either 16 or 32 (by changing CSR misa, for example),\nthen, whenever IALIGN=32, bit mnepc[1] is masked on reads so that it appears to be 0. This\nmasking occurs also for the implicit read by the MRET instruction. Though masked, mnepc[1]\nremains writable when IALIGN=32.\n\nmnepc is a WARL register that must be able to hold all valid virtual addresses. It need not be\ncapable of holding all possible invalid addresses. Prior to writing mnepc, implementations may\nconvert an invalid address into some other invalid address that mnepc is capable of holding.', 'address': 1857, 'priv_mode': 'M', 'reset-val': 0}, 'mncause': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': 'The mncause CSR holds the reason for the NMI, with bit MXLEN-1 set to 1, \nand the NMI cause encoded in the least-significant bits or zero if NMI causes are not supported.', 'address': 1858, 'priv_mode': 'M', 'reset-val': 2147483648}, 'mnstatus': {'rv32': {'accessible': False}, 'rv64': {'accessible': False}, 'description': '\nThe mnstatus CSR holds a two-bit field, MNPP, which on entry to the trap handler holds the\nprivilege mode of the interrupted context, encoded in the same manner as mstatus.MPP. It also\n\nholds a one-bit field, MNPV, which on entry to the trap handler holds the virtualization mode of\nthe interrupted context, encoded in the same manner as mstatus.MPV.\nmnstatus also holds the NMIE bit. When NMIE=1, nonmaskable interrupts are enabled. When\nNMIE=0, all interrupts are disabled.\nWhen NMIE=0, the hart behaves as though mstatus.MPRV were clear, regardless of the current\nsetting of mstatus.MPRV.\n\nUpon reset, NMIE contains the value 0.', 'address': 1860, 'priv_mode': 'M', 'reset-val': 0}, 'icache': {'reset-val': 1, 'rv64': {'accessible': False}, 'rv32': {'accessible': True, 'icache': {'implemented': True, 'type': {'rw': True}, 'description': 'bit for cache-enable of instruction cache', 'msb': 0, 'lsb': 0, 'shadow': None, 'shadow_type': None}, 'fields': ['icache', [[1, 31]]]}, 'description': 'the register controls the operation of the i-cache unit.', 'address': 1984, 'priv_mode': 'M'}, 'dcache': {'reset-val': 1, 'rv64': {'accessible': False}, 'rv32': {'accessible': True, 'dcache': {'implemented': True, 'type': {'rw': True}, 'description': 'bit for cache-enable of data cache', 'shadow': None, 'shadow_type': None, 'msb': 0, 'lsb': 0}, 'fields': ['dcache', [[1, 31]]]}, 'description': 'the register controls the operation of the d-cache unit.', 'address': 1985, 'priv_mode': 'M'}} ['mhpmcounter[3-31]', 'mhpmcounter[3-31]h'] writing file ./cv32a65x/csr/csr.adoc cp -r ../../design//../../config/gen_from_riscv_config/cv32a65x/* build/source cd ../.. && python3 scripts/spec_builder.py --target cv32a65x --gen-config /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/config.adoc --gen-parameters /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/parameters.adoc --gen-ports /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source Input file ../core/include/config_pkg.sv File /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/parameters.adoc written File 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Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_decoder.adoc Input file ../core/compressed_decoder.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_compressed_decoder.adoc Input file ../core/scoreboard.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_scoreboard.adoc Input file ../core/issue_read_operands.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_issue_read_operands.adoc Input file ../core/alu.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_alu.adoc Input file ../core/branch_unit.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_branch_unit.adoc Input file ../core/csr_buffer.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_csr_buffer.adoc Input file ../core/mult.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_mult.adoc Input file ../core/multiplier.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_multiplier.adoc Input file ../core/serdiv.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_serdiv.adoc Input file ../core/load_store_unit.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_load_store_unit.adoc Input file ../core/load_unit.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_load_unit.adoc Input file ../core/store_unit.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_store_unit.adoc Input file ../core/lsu_bypass.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_lsu_bypass.adoc Input file ../core/cvxif_fu.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_cvxif_fu.adoc Input file ../core/cache_subsystem/cva6_hpdcache_subsystem.sv Output file /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build/source/port_cva6_hpdcache_subsystem.adoc cd build; make SKIP_DOCKER=true build/design.html make[2]: Entering directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build' rm -rf build/design.html.workdir && mkdir -p build/design.html.workdir && cp -r source docs-resources build/design.html.workdir cd build/design.html.workdir && LANG=C.utf8 asciidoctor --trace -a compress -a mathematical-format=svg -a pdf-fontsdir=docs-resources/fonts -a pdf-theme=docs-resources/themes/riscv-pdf.yml -D build --failure-level=WARN -a attribute-missing=warn source/design.adoc mv build/design.html.workdir/build/design.html build/design.html && rm -rf build/design.html.workdir make[2]: Leaving directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design/build' cp ./build/build/design.html design-cv32a65x.html make[1]: Leaving directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/design' make -C 06_cv64a6_mmu/riscv priv-html unpriv-html make[1]: Entering directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/06_cv64a6_mmu/riscv' mkdir -p build/riscv-isa-manual cp -r ../../riscv-isa//riscv-isa-manual/* build/riscv-isa-manual cp -r ../../riscv-isa//src build/riscv-isa-manual cp ../../riscv-isa//../common/*.adoc build/riscv-isa-manual/src cd ../.. && python3 scripts/spec_builder.py --target cv64a6_mmu --gen-config /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/06_cv64a6_mmu/riscv/build/riscv-isa-manual/src/config.adoc Input file ../core/include/config_pkg.sv File /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/06_cv64a6_mmu/riscv/build/riscv-isa-manual/src/config.adoc written cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-privileged.html make[2]: Entering directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/06_cv64a6_mmu/riscv/build/riscv-isa-manual' rm -rf build/riscv-privileged.html.workdir && mkdir -p build/riscv-privileged.html.workdir && ln -sfn ../../src ../../docs-resources build/riscv-privileged.html.workdir/ cd build/riscv-privileged.html.workdir && LANG=C.utf8 asciidoctor --trace -a compress -a mathematical-format=svg -a pdf-fontsdir=docs-resources/fonts -a pdf-theme=docs-resources/themes/riscv-pdf.yml -D build --failure-level=ERROR --require=asciidoctor-bibtex --require=asciidoctor-diagram --require=asciidoctor-lists --require=asciidoctor-mathematical src/riscv-privileged.adoc mv build/riscv-privileged.html.workdir/build/riscv-privileged.html build/riscv-privileged.html && rm -rf build/riscv-privileged.html.workdir make[2]: Leaving directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/06_cv64a6_mmu/riscv/build/riscv-isa-manual' cp ./build/riscv-isa-manual/build/riscv-privileged.html priv-isa-cv64a6_mmu.html cd build/riscv-isa-manual; make SKIP_DOCKER=true build/riscv-unprivileged.html make[2]: Entering directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/06_cv64a6_mmu/riscv/build/riscv-isa-manual' rm -rf build/riscv-unprivileged.html.workdir && mkdir -p build/riscv-unprivileged.html.workdir && ln -sfn ../../src ../../docs-resources build/riscv-unprivileged.html.workdir/ cd build/riscv-unprivileged.html.workdir && LANG=C.utf8 asciidoctor --trace -a compress -a mathematical-format=svg -a pdf-fontsdir=docs-resources/fonts -a pdf-theme=docs-resources/themes/riscv-pdf.yml -D build --failure-level=ERROR --require=asciidoctor-bibtex --require=asciidoctor-diagram --require=asciidoctor-lists --require=asciidoctor-mathematical src/riscv-unprivileged.adoc mv build/riscv-unprivileged.html.workdir/build/riscv-unprivileged.html build/riscv-unprivileged.html && rm -rf build/riscv-unprivileged.html.workdir make[2]: Leaving directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/06_cv64a6_mmu/riscv/build/riscv-isa-manual' cp ./build/riscv-isa-manual/build/riscv-unprivileged.html unpriv-isa-cv64a6_mmu.html make[1]: Leaving directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/06_cv64a6_mmu/riscv' make: Leaving directory '/home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs' [rtd-command-info] start-time: 2025-01-26T20:56:19.682603Z, end-time: 2025-01-26T20:56:19.736458Z, duration: 0, exit-code: 0 cat docs/conf.py # Configuration file for the Sphinx documentation builder. # # This file only contains a selection of the most common options. For a full # list see the documentation: # https://www.sphinx-doc.org/en/master/usage/configuration.html # -- Path setup -------------------------------------------------------------- # If extensions (or modules to document with autodoc) are in another directory, # add these directories to sys.path here. If the directory is relative to the # documentation root, use os.path.abspath to make it absolute, like shown here. # # import os # import sys # sys.path.insert(0, os.path.abspath('.')) # -- Project information ----------------------------------------------------- project = 'CVA6' copyright = '2017-2020, ETH Zurich and University of Bologna, 2020-present OpenHW Group' author = 'OpenHW contributors' # -- General configuration --------------------------------------------------- # Add any Sphinx extension module names here, as strings. They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom # ones. extensions = [ 'recommonmark' ] # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates'] # List of patterns, relative to source directory, that match files and # directories to ignore when looking for source files. # This pattern also affects html_static_path and html_extra_path. exclude_patterns = ['_build', '**/build', 'Thumbs.db', '.DS_Store', '*.yaml', '*.xml', 'csr-from-ip-xact/**/*_csr.md', 'csr-ip-xact/**/cva6_csr.*'] # -- Options for HTML output ------------------------------------------------- # The theme to use for HTML and HTML Help pages. See the documentation for # a list of builtin themes. # #html_theme = 'alabaster' html_theme = 'sphinx_rtd_theme' pygments_style = 'monokai' # Theme options are theme-specific and customize the look and feel of a theme # further. For a list of options available for each theme, see the # documentation. # html_theme_options = {'style_nav_header_background': '#DDDDDD'} html_logo = '_static/openhw-landscape.svg' # Add any paths that contain custom static files (such as style sheets) here, # relative to this directory. They are copied after the builtin static files, # so a file named "default.css" will overwrite the builtin "default.css". #html_static_path = ['ystatic'] # Set html_static_path to null on the advice of RTDs: html_static_path = ['_static'] # Add customm CSS and JS files html_css_files = ['theme_overrides.css'] html_js_files = [] # Custom sidebar templates, must be a dictionary that maps document names # to template names. # # The default sidebars (for documents that don't match any pattern) are # defined by theme itself. Builtin themes are using these templates by # default: ``['localtoc.html', 'relations.html', 'sourcelink.html', # 'searchbox.html']``. # # html_sidebars = {} master_doc = 'index' [rtd-command-info] start-time: 2025-01-26T20:56:19.822280Z, end-time: 2025-01-26T20:56:30.654674Z, duration: 10, exit-code: 0 python -m sphinx -T -b html -d _build/doctrees -D language=en . $READTHEDOCS_OUTPUT/html Running Sphinx v7.4.7 loading translations [en]... done making output directory... done building [mo]: targets for 0 po files that are out of date writing output... building [html]: targets for 70 source files that are out of date updating environment: [new config] 70 added, 0 changed, 0 removed reading sources... [ 1%] 01_cva6_user/AXI_Interface reading sources... [ 3%] 01_cva6_user/CSR_CV32A60AX reading sources... [ 4%] 01_cva6_user/CSR_CV32A60AX_list reading sources... [ 6%] 01_cva6_user/CSR_CV32A60X reading sources... [ 7%] 01_cva6_user/CSR_CV32A60X_list reading sources... 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[ 99%] riscv-isa/riscv-isa-manual/docs-resources/README /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/envs/latest/lib/python3.9/site-packages/recommonmark/parser.py:75: UserWarning: Container node skipped: type=document warn("Container node skipped: type={0}".format(mdnode.t)) reading sources... [100%] riscv-isa/riscv-isa-manual/marchid /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/envs/latest/lib/python3.9/site-packages/recommonmark/parser.py:75: UserWarning: Container node skipped: type=document warn("Container node skipped: type={0}".format(mdnode.t)) csr-from-ip-xact/cv32a60x/csr.rst:9: WARNING: Title underline too short. REGISTERS CSR CV32A6 =================== csr-from-ip-xact/cv32a60x/csr.rst:11: WARNING: Title underline too short. Unimplemented CSR accessing generates an illegal instruction exception. -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:13: WARNING: Title underline too short. Read-Only CSR write access generates an illegal instruction exception. -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:13: WARNING: Title underline too short. Read-Only CSR write access generates an illegal instruction exception. -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:16: WARNING: Title underline too short. MSTATUS:Machine Status Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:16: WARNING: Title underline too short. MSTATUS:Machine Status Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:38: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:50: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:56: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:62: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:68: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:74: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:86: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:92: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:98: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:110: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:116: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:122: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:128: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:140: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:152: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:183: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:189: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:195: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:198: WARNING: Title underline too short. MIE:Machine Interrupt Enable Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:198: WARNING: Title underline too short. MIE:Machine Interrupt Enable Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:220: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:232: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:244: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:256: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:268: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:280: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:292: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:295: WARNING: Title underline too short. MTVEC:Machine Trap Vector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:295: WARNING: Title underline too short. MTVEC:Machine Trap Vector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:323: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:323: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:326: WARNING: Title underline too short. MSTATUSH:Upper 32-bits of Machine Status Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:326: WARNING: Title underline too short. MSTATUSH:Upper 32-bits of Machine Status Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:354: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:360: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:369: WARNING: Title underline too short. MHPMEVENT3:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:369: WARNING: Title underline too short. MHPMEVENT3:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:394: WARNING: Title underline too short. MHPMEVENT4:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:394: WARNING: Title underline too short. MHPMEVENT4:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:419: WARNING: Title underline too short. MHPMEVENT5:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:419: WARNING: Title underline too short. MHPMEVENT5:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:444: WARNING: Title underline too short. MHPMEVENT6:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:444: WARNING: Title underline too short. MHPMEVENT6:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:469: WARNING: Title underline too short. MHPMEVENT7:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:469: WARNING: Title underline too short. MHPMEVENT7:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:494: WARNING: Title underline too short. MHPMEVENT8:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:494: WARNING: Title underline too short. MHPMEVENT8:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:519: WARNING: Title underline too short. MHPMEVENT9:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:519: WARNING: Title underline too short. MHPMEVENT9:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:544: WARNING: Title underline too short. MHPMEVENT10:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:544: WARNING: Title underline too short. MHPMEVENT10:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:569: WARNING: Title underline too short. MHPMEVENT11:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:569: WARNING: Title underline too short. MHPMEVENT11:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:594: WARNING: Title underline too short. MHPMEVENT12:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:594: WARNING: Title underline too short. MHPMEVENT12:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:619: WARNING: Title underline too short. MHPMEVENT13:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:619: WARNING: Title underline too short. MHPMEVENT13:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:644: WARNING: Title underline too short. MHPMEVENT14:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:644: WARNING: Title underline too short. MHPMEVENT14:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:669: WARNING: Title underline too short. MHPMEVENT15:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:669: WARNING: Title underline too short. MHPMEVENT15:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:694: WARNING: Title underline too short. MHPMEVENT16:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:694: WARNING: Title underline too short. MHPMEVENT16:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:719: WARNING: Title underline too short. MHPMEVENT17:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:719: WARNING: Title underline too short. MHPMEVENT17:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:744: WARNING: Title underline too short. MHPMEVENT18:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:744: WARNING: Title underline too short. MHPMEVENT18:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:769: WARNING: Title underline too short. MHPMEVENT19:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:769: WARNING: Title underline too short. MHPMEVENT19:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:794: WARNING: Title underline too short. MHPMEVENT20:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:794: WARNING: Title underline too short. MHPMEVENT20:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:819: WARNING: Title underline too short. MHPMEVENT21:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:819: WARNING: Title underline too short. MHPMEVENT21:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:844: WARNING: Title underline too short. MHPMEVENT22:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:844: WARNING: Title underline too short. MHPMEVENT22:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:869: WARNING: Title underline too short. MHPMEVENT23:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:869: WARNING: Title underline too short. MHPMEVENT23:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:894: WARNING: Title underline too short. MHPMEVENT24:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:894: WARNING: Title underline too short. MHPMEVENT24:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:919: WARNING: Title underline too short. MHPMEVENT25:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:919: WARNING: Title underline too short. MHPMEVENT25:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:944: WARNING: Title underline too short. MHPMEVENT26:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:944: WARNING: Title underline too short. MHPMEVENT26:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:969: WARNING: Title underline too short. MHPMEVENT27:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:969: WARNING: Title underline too short. MHPMEVENT27:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:994: WARNING: Title underline too short. MHPMEVENT28:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:994: WARNING: Title underline too short. MHPMEVENT28:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1019: WARNING: Title underline too short. MHPMEVENT29:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1019: WARNING: Title underline too short. MHPMEVENT29:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1044: WARNING: Title underline too short. MHPMEVENT30:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1044: WARNING: Title underline too short. MHPMEVENT30:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1069: WARNING: Title underline too short. MHPMEVENT31:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1069: WARNING: Title underline too short. MHPMEVENT31:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1094: WARNING: Title underline too short. MSCRATCH:Machine Scratch Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1094: WARNING: Title underline too short. MSCRATCH:Machine Scratch Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1119: WARNING: Title underline too short. MEPC:Machine Exception Program Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1119: WARNING: Title underline too short. MEPC:Machine Exception Program Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1144: WARNING: Title underline too short. MCAUSE:Machine Cause Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1144: WARNING: Title underline too short. MCAUSE:Machine Cause Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1269: WARNING: Title underline too short. MTVAL:Machine Trap Value Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1269: WARNING: Title underline too short. MTVAL:Machine Trap Value Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1294: WARNING: Title underline too short. MIP:Machine Interrupt Pending Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1294: WARNING: Title underline too short. MIP:Machine Interrupt Pending Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1316: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:1328: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:1340: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:1352: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:1364: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:1376: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:1388: WARNING: Inline literal start-string without end-string. csr-from-ip-xact/cv32a60x/csr.rst:1391: WARNING: Title underline too short. PMPCFG0:Physical Memory Protection Config 0 Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1391: WARNING: Title underline too short. PMPCFG0:Physical Memory Protection Config 0 Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1434: WARNING: Title underline too short. PMPCFG1:Physical Memory Protection Config 1 Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1434: WARNING: Title underline too short. PMPCFG1:Physical Memory Protection Config 1 Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1477: WARNING: Title underline too short. PMPCFG2:Physical Memory Protection Config 2 Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1477: WARNING: Title underline too short. PMPCFG2:Physical Memory Protection Config 2 Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1520: WARNING: Title underline too short. PMPCFG3:Physical Memory Protection Config 3 Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1520: WARNING: Title underline too short. PMPCFG3:Physical Memory Protection Config 3 Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1563: WARNING: Title underline too short. PMPADDR0:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1563: WARNING: Title underline too short. PMPADDR0:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1588: WARNING: Title underline too short. PMPADDR1:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1588: WARNING: Title underline too short. PMPADDR1:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1613: WARNING: Title underline too short. PMPADDR2:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1613: WARNING: Title underline too short. PMPADDR2:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1638: WARNING: Title underline too short. PMPADDR3:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1638: WARNING: Title underline too short. PMPADDR3:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1663: WARNING: Title underline too short. PMPADDR4:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1663: WARNING: Title underline too short. PMPADDR4:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1688: WARNING: Title underline too short. PMPADDR5:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1688: WARNING: Title underline too short. PMPADDR5:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1713: WARNING: Title underline too short. PMPADDR6:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1713: WARNING: Title underline too short. PMPADDR6:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1738: WARNING: Title underline too short. PMPADDR7:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1738: WARNING: Title underline too short. PMPADDR7:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1763: WARNING: Title underline too short. PMPADDR8:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1763: WARNING: Title underline too short. PMPADDR8:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1788: WARNING: Title underline too short. PMPADDR9:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1788: WARNING: Title underline too short. PMPADDR9:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1813: WARNING: Title underline too short. PMPADDR10:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1813: WARNING: Title underline too short. PMPADDR10:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1838: WARNING: Title underline too short. PMPADDR11:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1838: WARNING: Title underline too short. PMPADDR11:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1863: WARNING: Title underline too short. PMPADDR12:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1863: WARNING: Title underline too short. PMPADDR12:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1888: WARNING: Title underline too short. PMPADDR13:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1888: WARNING: Title underline too short. PMPADDR13:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1913: WARNING: Title underline too short. PMPADDR14:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1913: WARNING: Title underline too short. PMPADDR14:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1938: WARNING: Title underline too short. PMPADDR15:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1938: WARNING: Title underline too short. PMPADDR15:Physical Memory Protection Address Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1963: WARNING: Title underline too short. ICACHE:Instruction Cache Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1963: WARNING: Title underline too short. ICACHE:Instruction Cache Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1994: WARNING: Title underline too short. MCYCLE:M-mode Cycle counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:1994: WARNING: Title underline too short. MCYCLE:M-mode Cycle counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2019: WARNING: Title underline too short. MINSTRET:Machine Instruction Retired counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2019: WARNING: Title underline too short. MINSTRET:Machine Instruction Retired counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2044: WARNING: Title underline too short. MCYCLEH:Upper 32-bits of M-mode Cycle counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2044: WARNING: Title underline too short. MCYCLEH:Upper 32-bits of M-mode Cycle counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2069: WARNING: Title underline too short. MINSTRETH:Upper 32-bits of Machine Instruction Retired counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2069: WARNING: Title underline too short. MINSTRETH:Upper 32-bits of Machine Instruction Retired counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2094: WARNING: Title underline too short. MHPMCOUNTER3:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2094: WARNING: Title underline too short. MHPMCOUNTER3:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2119: WARNING: Title underline too short. MHPMCOUNTER4:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2119: WARNING: Title underline too short. MHPMCOUNTER4:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2144: WARNING: Title underline too short. MHPMCOUNTER5:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2144: WARNING: Title underline too short. MHPMCOUNTER5:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2169: WARNING: Title underline too short. MHPMCOUNTER6:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2169: WARNING: Title underline too short. MHPMCOUNTER6:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2194: WARNING: Title underline too short. MHPMCOUNTER7:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2194: WARNING: Title underline too short. MHPMCOUNTER7:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2219: WARNING: Title underline too short. MHPMCOUNTER8:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2219: WARNING: Title underline too short. MHPMCOUNTER8:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2244: WARNING: Title underline too short. MHPMCOUNTER9:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2244: WARNING: Title underline too short. MHPMCOUNTER9:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2269: WARNING: Title underline too short. MHPMCOUNTER10:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2269: WARNING: Title underline too short. MHPMCOUNTER10:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2294: WARNING: Title underline too short. MHPMCOUNTER11:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2294: WARNING: Title underline too short. MHPMCOUNTER11:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2319: WARNING: Title underline too short. MHPMCOUNTER12:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2319: WARNING: Title underline too short. MHPMCOUNTER12:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2344: WARNING: Title underline too short. MHPMCOUNTER13:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2344: WARNING: Title underline too short. MHPMCOUNTER13:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2369: WARNING: Title underline too short. MHPMCOUNTER14:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2369: WARNING: Title underline too short. MHPMCOUNTER14:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2394: WARNING: Title underline too short. MHPMCOUNTER15:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2394: WARNING: Title underline too short. MHPMCOUNTER15:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2419: WARNING: Title underline too short. MHPMCOUNTER16:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2419: WARNING: Title underline too short. MHPMCOUNTER16:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2444: WARNING: Title underline too short. MHPMCOUNTER17:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2444: WARNING: Title underline too short. MHPMCOUNTER17:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2469: WARNING: Title underline too short. MHPMCOUNTER18:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2469: WARNING: Title underline too short. MHPMCOUNTER18:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2494: WARNING: Title underline too short. MHPMCOUNTER19:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2494: WARNING: Title underline too short. MHPMCOUNTER19:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2519: WARNING: Title underline too short. MHPMCOUNTER20:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2519: WARNING: Title underline too short. MHPMCOUNTER20:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2544: WARNING: Title underline too short. MHPMCOUNTER21:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2544: WARNING: Title underline too short. MHPMCOUNTER21:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2569: WARNING: Title underline too short. MHPMCOUNTER22:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2569: WARNING: Title underline too short. MHPMCOUNTER22:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2594: WARNING: Title underline too short. MHPMCOUNTER23:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2594: WARNING: Title underline too short. MHPMCOUNTER23:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2619: WARNING: Title underline too short. MHPMCOUNTER24:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2619: WARNING: Title underline too short. MHPMCOUNTER24:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2644: WARNING: Title underline too short. MHPMCOUNTER25:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2644: WARNING: Title underline too short. MHPMCOUNTER25:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2669: WARNING: Title underline too short. MHPMCOUNTER26:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2669: WARNING: Title underline too short. MHPMCOUNTER26:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2694: WARNING: Title underline too short. MHPMCOUNTER27:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2694: WARNING: Title underline too short. MHPMCOUNTER27:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2719: WARNING: Title underline too short. MHPMCOUNTER28:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2719: WARNING: Title underline too short. MHPMCOUNTER28:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2744: WARNING: Title underline too short. MHPMCOUNTER29:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2744: WARNING: Title underline too short. MHPMCOUNTER29:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2769: WARNING: Title underline too short. MHPMCOUNTER30:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2769: WARNING: Title underline too short. MHPMCOUNTER30:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2794: WARNING: Title underline too short. MHPMCOUNTER31:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2794: WARNING: Title underline too short. MHPMCOUNTER31:Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2819: WARNING: Title underline too short. MHPMCOUNTERH3:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2819: WARNING: Title underline too short. MHPMCOUNTERH3:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2844: WARNING: Title underline too short. MHPMCOUNTERH4:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2844: WARNING: Title underline too short. MHPMCOUNTERH4:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2869: WARNING: Title underline too short. MHPMCOUNTERH5:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2869: WARNING: Title underline too short. MHPMCOUNTERH5:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2894: WARNING: Title underline too short. MHPMCOUNTERH6:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2894: WARNING: Title underline too short. MHPMCOUNTERH6:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2919: WARNING: Title underline too short. MHPMCOUNTERH7:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2919: WARNING: Title underline too short. MHPMCOUNTERH7:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2944: WARNING: Title underline too short. MHPMCOUNTERH8:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2944: WARNING: Title underline too short. MHPMCOUNTERH8:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2969: WARNING: Title underline too short. MHPMCOUNTERH9:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2969: WARNING: Title underline too short. MHPMCOUNTERH9:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2994: WARNING: Title underline too short. MHPMCOUNTERH10:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:2994: WARNING: Title underline too short. MHPMCOUNTERH10:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3019: WARNING: Title underline too short. MHPMCOUNTERH11:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3019: WARNING: Title underline too short. MHPMCOUNTERH11:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3044: WARNING: Title underline too short. MHPMCOUNTERH12:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3044: WARNING: Title underline too short. MHPMCOUNTERH12:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3069: WARNING: Title underline too short. MHPMCOUNTERH13:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3069: WARNING: Title underline too short. MHPMCOUNTERH13:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3094: WARNING: Title underline too short. MHPMCOUNTERH14:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3094: WARNING: Title underline too short. MHPMCOUNTERH14:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3119: WARNING: Title underline too short. MHPMCOUNTERH15:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3119: WARNING: Title underline too short. MHPMCOUNTERH15:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3144: WARNING: Title underline too short. MHPMCOUNTERH16:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3144: WARNING: Title underline too short. MHPMCOUNTERH16:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3169: WARNING: Title underline too short. MHPMCOUNTERH17:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3169: WARNING: Title underline too short. MHPMCOUNTERH17:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3194: WARNING: Title underline too short. MHPMCOUNTERH18:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3194: WARNING: Title underline too short. MHPMCOUNTERH18:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3219: WARNING: Title underline too short. MHPMCOUNTERH19:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3219: WARNING: Title underline too short. MHPMCOUNTERH19:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3244: WARNING: Title underline too short. MHPMCOUNTERH20:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3244: WARNING: Title underline too short. MHPMCOUNTERH20:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3269: WARNING: Title underline too short. MHPMCOUNTERH21:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3269: WARNING: Title underline too short. MHPMCOUNTERH21:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3294: WARNING: Title underline too short. MHPMCOUNTERH22:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3294: WARNING: Title underline too short. MHPMCOUNTERH22:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3319: WARNING: Title underline too short. MHPMCOUNTERH23:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3319: WARNING: Title underline too short. MHPMCOUNTERH23:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3344: WARNING: Title underline too short. MHPMCOUNTERH24:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3344: WARNING: Title underline too short. MHPMCOUNTERH24:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3369: WARNING: Title underline too short. MHPMCOUNTERH25:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3369: WARNING: Title underline too short. MHPMCOUNTERH25:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3394: WARNING: Title underline too short. MHPMCOUNTERH26:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3394: WARNING: Title underline too short. MHPMCOUNTERH26:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3419: WARNING: Title underline too short. MHPMCOUNTERH27:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3419: WARNING: Title underline too short. MHPMCOUNTERH27:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3444: WARNING: Title underline too short. MHPMCOUNTERH28:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3444: WARNING: Title underline too short. MHPMCOUNTERH28:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3469: WARNING: Title underline too short. MHPMCOUNTERH29:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3469: WARNING: Title underline too short. MHPMCOUNTERH29:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3494: WARNING: Title underline too short. MHPMCOUNTERH30:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3494: WARNING: Title underline too short. MHPMCOUNTERH30:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3519: WARNING: Title underline too short. MHPMCOUNTERH31:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3519: WARNING: Title underline too short. MHPMCOUNTERH31:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3544: WARNING: Title underline too short. CYCLE:Cycle counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3544: WARNING: Title underline too short. CYCLE:Cycle counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3569: WARNING: Title underline too short. INSTRET:Instruction Retired counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3569: WARNING: Title underline too short. INSTRET:Instruction Retired counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3594: WARNING: Title underline too short. CYCLEH:Upper 32-bits of Cycle counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3594: WARNING: Title underline too short. CYCLEH:Upper 32-bits of Cycle counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3619: WARNING: Title underline too short. INSTRETH:Upper 32-bits of Instruction Retired counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3619: WARNING: Title underline too short. INSTRETH:Upper 32-bits of Instruction Retired counter Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3644: WARNING: Title underline too short. MVENDORID:Machine Vendor ID Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3644: WARNING: Title underline too short. MVENDORID:Machine Vendor ID Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3675: WARNING: Title underline too short. MARCHID:Machine Architecture ID Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3675: WARNING: Title underline too short. MARCHID:Machine Architecture ID Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3700: WARNING: Title underline too short. MIMPID:Machine Implementation ID Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3700: WARNING: Title underline too short. MIMPID:Machine Implementation ID Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3725: WARNING: Title underline too short. MHARTID:Machine Hardware Thread ID Register -------------------------- csr-from-ip-xact/cv32a60x/csr.rst:3725: WARNING: Title underline too short. MHARTID:Machine Hardware Thread ID Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/CSR_CV64A6_MMU.rst:23: WARNING: Title underline too short. CV64A6_MMU Control Status Registers ================================== /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/CSR_CV64A6_MMU_list.rst:23: WARNING: Title underline too short. CV64A6_MMU Control Status Registers List ======================================= /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Programmer_View.rst:112: WARNING: Title underline too short. CV64A6_MMU extensions ~~~~~~~~~~~~~~~~~~~ /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Programmer_View.rst:112: WARNING: Title underline too short. CV64A6_MMU extensions ~~~~~~~~~~~~~~~~~~~ /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Programmer_View.rst:185: WARNING: Title underline too short. CV64A6_MMU privilege modes ~~~~~~~~~~~~~~~~~~~~~~~~~ /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Programmer_View.rst:185: WARNING: Title underline too short. CV64A6_MMU privilege modes ~~~~~~~~~~~~~~~~~~~~~~~~~ /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Programmer_View.rst:249: WARNING: Title underline too short. CV64A6_MMU virtual memory ~~~~~~~~~~~~~~~~~~~~~~~~ /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Programmer_View.rst:249: WARNING: Title underline too short. CV64A6_MMU virtual memory ~~~~~~~~~~~~~~~~~~~~~~~~ /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst:31: WARNING: Title overline too short. ============================= RVZbkb: Bitmanip instructions for Cryptography ============================= /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst:119: WARNING: Block quote ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst:134: WARNING: Block quote ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst:142: WARNING: Title underline too short. Bits-in-Byte-reverse ------------ /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst:142: WARNING: Title underline too short. Bits-in-Byte-reverse ------------ /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst:163: WARNING: Definition list ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst:164: WARNING: Block quote ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:49: ERROR: Unexpected indentation. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:53: WARNING: Definition list ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:55: WARNING: Definition list ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:56: WARNING: Block quote ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:72: ERROR: Unexpected indentation. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:76: WARNING: Definition list ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:78: WARNING: Definition list ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:79: WARNING: Block quote ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:95: ERROR: Unexpected indentation. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:99: WARNING: Definition list ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:101: WARNING: Definition list ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:102: WARNING: Block quote ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:120: ERROR: Unexpected indentation. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:124: WARNING: Definition list ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:126: WARNING: Definition list ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:127: WARNING: Block quote ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:143: WARNING: Block quote ends without a blank line; unexpected unindent. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst:161: WARNING: Block quote ends without a blank line; unexpected unindent. WARNING: duplicate label cva6_user_cfg_doc, other instance in /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Parameters_Configuration.rst /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/06_cv64a6_mmu/index.rst:2: WARNING: Title underline too short. CV64A6_MMU documentation ====================== /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:9: WARNING: Title underline too short. REGISTERS CSR CV32A6 =================== /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:11: WARNING: Title underline too short. Unimplemented CSR accessing generates an illegal instruction exception. -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:13: WARNING: Title underline too short. Read-Only CSR write access generates an illegal instruction exception. -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:13: WARNING: Title underline too short. Read-Only CSR write access generates an illegal instruction exception. -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:16: WARNING: Title underline too short. MSTATUS:Machine Status Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:16: WARNING: Title underline too short. MSTATUS:Machine Status Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:38: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:50: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:56: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:62: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:68: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:74: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:86: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:92: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:98: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:110: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:116: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:122: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:128: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:140: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:152: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:183: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:189: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:195: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:198: WARNING: Title underline too short. MIE:Machine Interrupt Enable Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:198: WARNING: Title underline too short. MIE:Machine Interrupt Enable Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:220: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:232: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:244: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:256: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:268: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:280: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:292: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:295: WARNING: Title underline too short. MTVEC:Machine Trap Vector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:295: WARNING: Title underline too short. MTVEC:Machine Trap Vector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:323: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:323: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:326: WARNING: Title underline too short. MSTATUSH:Upper 32-bits of Machine Status Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:326: WARNING: Title underline too short. MSTATUSH:Upper 32-bits of Machine Status Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:354: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:360: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:369: WARNING: Title underline too short. MHPMEVENT3:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:369: WARNING: Title underline too short. MHPMEVENT3:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:394: WARNING: Title underline too short. MHPMEVENT4:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:394: WARNING: Title underline too short. MHPMEVENT4:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:419: WARNING: Title underline too short. MHPMEVENT5:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:419: WARNING: Title underline too short. MHPMEVENT5:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:444: WARNING: Title underline too short. MHPMEVENT6:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:444: WARNING: Title underline too short. MHPMEVENT6:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:469: WARNING: Title underline too short. MHPMEVENT7:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:469: WARNING: Title underline too short. MHPMEVENT7:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:494: WARNING: Title underline too short. MHPMEVENT8:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:494: WARNING: Title underline too short. MHPMEVENT8:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:519: WARNING: Title underline too short. MHPMEVENT9:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:519: WARNING: Title underline too short. MHPMEVENT9:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:544: WARNING: Title underline too short. MHPMEVENT10:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:544: WARNING: Title underline too short. MHPMEVENT10:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:569: WARNING: Title underline too short. MHPMEVENT11:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:569: WARNING: Title underline too short. MHPMEVENT11:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:594: WARNING: Title underline too short. MHPMEVENT12:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:594: WARNING: Title underline too short. MHPMEVENT12:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:619: WARNING: Title underline too short. MHPMEVENT13:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:619: WARNING: Title underline too short. MHPMEVENT13:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:644: WARNING: Title underline too short. MHPMEVENT14:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:644: WARNING: Title underline too short. MHPMEVENT14:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:669: WARNING: Title underline too short. MHPMEVENT15:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:669: WARNING: Title underline too short. MHPMEVENT15:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:694: WARNING: Title underline too short. MHPMEVENT16:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:694: WARNING: Title underline too short. MHPMEVENT16:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:719: WARNING: Title underline too short. MHPMEVENT17:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:719: WARNING: Title underline too short. MHPMEVENT17:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:744: WARNING: Title underline too short. MHPMEVENT18:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:744: WARNING: Title underline too short. MHPMEVENT18:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:769: WARNING: Title underline too short. MHPMEVENT19:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:769: WARNING: Title underline too short. MHPMEVENT19:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:794: WARNING: Title underline too short. MHPMEVENT20:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:794: WARNING: Title underline too short. MHPMEVENT20:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:819: WARNING: Title underline too short. MHPMEVENT21:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:819: WARNING: Title underline too short. MHPMEVENT21:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:844: WARNING: Title underline too short. MHPMEVENT22:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:844: WARNING: Title underline too short. MHPMEVENT22:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:869: WARNING: Title underline too short. MHPMEVENT23:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:869: WARNING: Title underline too short. MHPMEVENT23:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:894: WARNING: Title underline too short. MHPMEVENT24:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:894: WARNING: Title underline too short. MHPMEVENT24:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:919: WARNING: Title underline too short. MHPMEVENT25:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:919: WARNING: Title underline too short. MHPMEVENT25:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:944: WARNING: Title underline too short. MHPMEVENT26:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:944: WARNING: Title underline too short. MHPMEVENT26:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:969: WARNING: Title underline too short. MHPMEVENT27:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:969: WARNING: Title underline too short. MHPMEVENT27:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:994: WARNING: Title underline too short. MHPMEVENT28:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:994: WARNING: Title underline too short. MHPMEVENT28:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1019: WARNING: Title underline too short. MHPMEVENT29:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1019: WARNING: Title underline too short. MHPMEVENT29:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1044: WARNING: Title underline too short. MHPMEVENT30:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1044: WARNING: Title underline too short. MHPMEVENT30:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1069: WARNING: Title underline too short. MHPMEVENT31:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1069: WARNING: Title underline too short. MHPMEVENT31:Machine Hardware Performance-Monitoring Event Selector Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1094: WARNING: Title underline too short. MSCRATCH:Machine Scratch Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1094: WARNING: Title underline too short. MSCRATCH:Machine Scratch Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1119: WARNING: Title underline too short. MEPC:Machine Exception Program Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1119: WARNING: Title underline too short. MEPC:Machine Exception Program Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1144: WARNING: Title underline too short. MCAUSE:Machine Cause Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1144: WARNING: Title underline too short. MCAUSE:Machine Cause Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1269: WARNING: Title underline too short. MTVAL:Machine Trap Value Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1269: WARNING: Title underline too short. MTVAL:Machine Trap Value Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1294: WARNING: Title underline too short. MIP:Machine Interrupt Pending Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1294: WARNING: Title underline too short. MIP:Machine Interrupt Pending Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1316: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1328: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1340: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1352: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1364: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1376: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1388: WARNING: Inline literal start-string without end-string. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1391: WARNING: Title underline too short. PMPCFG0:Physical Memory Protection Config 0 Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1391: WARNING: Title underline too short. PMPCFG0:Physical Memory Protection Config 0 Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1434: WARNING: Title underline too short. PMPCFG1:Physical Memory Protection Config 1 Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1434: WARNING: Title underline too short. PMPCFG1:Physical Memory Protection Config 1 Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1477: WARNING: Title underline too short. PMPCFG2:Physical Memory Protection Config 2 Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1477: WARNING: Title underline too short. PMPCFG2:Physical Memory Protection Config 2 Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1520: WARNING: Title underline too short. PMPCFG3:Physical Memory Protection Config 3 Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1520: WARNING: Title underline too short. PMPCFG3:Physical Memory Protection Config 3 Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1563: WARNING: Title underline too short. PMPADDR0:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1563: WARNING: Title underline too short. PMPADDR0:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1588: WARNING: Title underline too short. PMPADDR1:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1588: WARNING: Title underline too short. PMPADDR1:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1613: WARNING: Title underline too short. PMPADDR2:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1613: WARNING: Title underline too short. PMPADDR2:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1638: WARNING: Title underline too short. PMPADDR3:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1638: WARNING: Title underline too short. PMPADDR3:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1663: WARNING: Title underline too short. PMPADDR4:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1663: WARNING: Title underline too short. PMPADDR4:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1688: WARNING: Title underline too short. PMPADDR5:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1688: WARNING: Title underline too short. PMPADDR5:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1713: WARNING: Title underline too short. PMPADDR6:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1713: WARNING: Title underline too short. PMPADDR6:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1738: WARNING: Title underline too short. PMPADDR7:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1738: WARNING: Title underline too short. PMPADDR7:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1763: WARNING: Title underline too short. PMPADDR8:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1763: WARNING: Title underline too short. PMPADDR8:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1788: WARNING: Title underline too short. PMPADDR9:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1788: WARNING: Title underline too short. PMPADDR9:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1813: WARNING: Title underline too short. PMPADDR10:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1813: WARNING: Title underline too short. PMPADDR10:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1838: WARNING: Title underline too short. PMPADDR11:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1838: WARNING: Title underline too short. PMPADDR11:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1863: WARNING: Title underline too short. PMPADDR12:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1863: WARNING: Title underline too short. PMPADDR12:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1888: WARNING: Title underline too short. PMPADDR13:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1888: WARNING: Title underline too short. PMPADDR13:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1913: WARNING: Title underline too short. PMPADDR14:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1913: WARNING: Title underline too short. PMPADDR14:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1938: WARNING: Title underline too short. PMPADDR15:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1938: WARNING: Title underline too short. PMPADDR15:Physical Memory Protection Address Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1963: WARNING: Title underline too short. ICACHE:Instruction Cache Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1963: WARNING: Title underline too short. ICACHE:Instruction Cache Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1994: WARNING: Title underline too short. MCYCLE:M-mode Cycle counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:1994: WARNING: Title underline too short. MCYCLE:M-mode Cycle counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2019: WARNING: Title underline too short. MINSTRET:Machine Instruction Retired counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2019: WARNING: Title underline too short. MINSTRET:Machine Instruction Retired counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2044: WARNING: Title underline too short. MCYCLEH:Upper 32-bits of M-mode Cycle counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2044: WARNING: Title underline too short. MCYCLEH:Upper 32-bits of M-mode Cycle counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2069: WARNING: Title underline too short. MINSTRETH:Upper 32-bits of Machine Instruction Retired counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2069: WARNING: Title underline too short. MINSTRETH:Upper 32-bits of Machine Instruction Retired counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2094: WARNING: Title underline too short. MHPMCOUNTER3:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2094: WARNING: Title underline too short. MHPMCOUNTER3:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2119: WARNING: Title underline too short. MHPMCOUNTER4:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2119: WARNING: Title underline too short. MHPMCOUNTER4:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2144: WARNING: Title underline too short. MHPMCOUNTER5:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2144: WARNING: Title underline too short. MHPMCOUNTER5:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2169: WARNING: Title underline too short. MHPMCOUNTER6:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2169: WARNING: Title underline too short. MHPMCOUNTER6:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2194: WARNING: Title underline too short. MHPMCOUNTER7:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2194: WARNING: Title underline too short. MHPMCOUNTER7:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2219: WARNING: Title underline too short. MHPMCOUNTER8:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2219: WARNING: Title underline too short. MHPMCOUNTER8:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2244: WARNING: Title underline too short. MHPMCOUNTER9:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2244: WARNING: Title underline too short. MHPMCOUNTER9:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2269: WARNING: Title underline too short. MHPMCOUNTER10:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2269: WARNING: Title underline too short. MHPMCOUNTER10:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2294: WARNING: Title underline too short. MHPMCOUNTER11:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2294: WARNING: Title underline too short. MHPMCOUNTER11:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2319: WARNING: Title underline too short. MHPMCOUNTER12:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2319: WARNING: Title underline too short. MHPMCOUNTER12:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2344: WARNING: Title underline too short. MHPMCOUNTER13:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2344: WARNING: Title underline too short. MHPMCOUNTER13:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2369: WARNING: Title underline too short. MHPMCOUNTER14:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2369: WARNING: Title underline too short. MHPMCOUNTER14:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2394: WARNING: Title underline too short. MHPMCOUNTER15:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2394: WARNING: Title underline too short. MHPMCOUNTER15:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2419: WARNING: Title underline too short. MHPMCOUNTER16:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2419: WARNING: Title underline too short. MHPMCOUNTER16:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2444: WARNING: Title underline too short. MHPMCOUNTER17:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2444: WARNING: Title underline too short. MHPMCOUNTER17:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2469: WARNING: Title underline too short. MHPMCOUNTER18:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2469: WARNING: Title underline too short. MHPMCOUNTER18:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2494: WARNING: Title underline too short. MHPMCOUNTER19:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2494: WARNING: Title underline too short. MHPMCOUNTER19:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2519: WARNING: Title underline too short. MHPMCOUNTER20:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2519: WARNING: Title underline too short. MHPMCOUNTER20:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2544: WARNING: Title underline too short. MHPMCOUNTER21:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2544: WARNING: Title underline too short. MHPMCOUNTER21:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2569: WARNING: Title underline too short. MHPMCOUNTER22:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2569: WARNING: Title underline too short. MHPMCOUNTER22:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2594: WARNING: Title underline too short. MHPMCOUNTER23:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2594: WARNING: Title underline too short. MHPMCOUNTER23:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2619: WARNING: Title underline too short. MHPMCOUNTER24:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2619: WARNING: Title underline too short. MHPMCOUNTER24:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2644: WARNING: Title underline too short. MHPMCOUNTER25:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2644: WARNING: Title underline too short. MHPMCOUNTER25:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2669: WARNING: Title underline too short. MHPMCOUNTER26:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2669: WARNING: Title underline too short. MHPMCOUNTER26:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2694: WARNING: Title underline too short. MHPMCOUNTER27:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2694: WARNING: Title underline too short. MHPMCOUNTER27:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2719: WARNING: Title underline too short. MHPMCOUNTER28:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2719: WARNING: Title underline too short. MHPMCOUNTER28:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2744: WARNING: Title underline too short. MHPMCOUNTER29:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2744: WARNING: Title underline too short. MHPMCOUNTER29:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2769: WARNING: Title underline too short. MHPMCOUNTER30:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2769: WARNING: Title underline too short. MHPMCOUNTER30:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2794: WARNING: Title underline too short. MHPMCOUNTER31:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2794: WARNING: Title underline too short. MHPMCOUNTER31:Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2819: WARNING: Title underline too short. MHPMCOUNTERH3:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2819: WARNING: Title underline too short. MHPMCOUNTERH3:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2844: WARNING: Title underline too short. MHPMCOUNTERH4:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2844: WARNING: Title underline too short. MHPMCOUNTERH4:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2869: WARNING: Title underline too short. MHPMCOUNTERH5:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2869: WARNING: Title underline too short. MHPMCOUNTERH5:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2894: WARNING: Title underline too short. MHPMCOUNTERH6:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2894: WARNING: Title underline too short. MHPMCOUNTERH6:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2919: WARNING: Title underline too short. MHPMCOUNTERH7:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2919: WARNING: Title underline too short. MHPMCOUNTERH7:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2944: WARNING: Title underline too short. MHPMCOUNTERH8:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2944: WARNING: Title underline too short. MHPMCOUNTERH8:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2969: WARNING: Title underline too short. MHPMCOUNTERH9:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2969: WARNING: Title underline too short. MHPMCOUNTERH9:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2994: WARNING: Title underline too short. MHPMCOUNTERH10:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:2994: WARNING: Title underline too short. MHPMCOUNTERH10:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3019: WARNING: Title underline too short. MHPMCOUNTERH11:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3019: WARNING: Title underline too short. MHPMCOUNTERH11:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3044: WARNING: Title underline too short. MHPMCOUNTERH12:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3044: WARNING: Title underline too short. MHPMCOUNTERH12:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3069: WARNING: Title underline too short. MHPMCOUNTERH13:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3069: WARNING: Title underline too short. MHPMCOUNTERH13:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3094: WARNING: Title underline too short. MHPMCOUNTERH14:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3094: WARNING: Title underline too short. MHPMCOUNTERH14:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3119: WARNING: Title underline too short. MHPMCOUNTERH15:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3119: WARNING: Title underline too short. MHPMCOUNTERH15:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3144: WARNING: Title underline too short. MHPMCOUNTERH16:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3144: WARNING: Title underline too short. MHPMCOUNTERH16:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3169: WARNING: Title underline too short. MHPMCOUNTERH17:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3169: WARNING: Title underline too short. MHPMCOUNTERH17:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3194: WARNING: Title underline too short. MHPMCOUNTERH18:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3194: WARNING: Title underline too short. MHPMCOUNTERH18:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3219: WARNING: Title underline too short. MHPMCOUNTERH19:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3219: WARNING: Title underline too short. MHPMCOUNTERH19:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3244: WARNING: Title underline too short. MHPMCOUNTERH20:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3244: WARNING: Title underline too short. MHPMCOUNTERH20:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3269: WARNING: Title underline too short. MHPMCOUNTERH21:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3269: WARNING: Title underline too short. MHPMCOUNTERH21:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3294: WARNING: Title underline too short. MHPMCOUNTERH22:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3294: WARNING: Title underline too short. MHPMCOUNTERH22:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3319: WARNING: Title underline too short. MHPMCOUNTERH23:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3319: WARNING: Title underline too short. MHPMCOUNTERH23:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3344: WARNING: Title underline too short. MHPMCOUNTERH24:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3344: WARNING: Title underline too short. MHPMCOUNTERH24:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3369: WARNING: Title underline too short. MHPMCOUNTERH25:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3369: WARNING: Title underline too short. MHPMCOUNTERH25:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3394: WARNING: Title underline too short. MHPMCOUNTERH26:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3394: WARNING: Title underline too short. MHPMCOUNTERH26:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3419: WARNING: Title underline too short. MHPMCOUNTERH27:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3419: WARNING: Title underline too short. MHPMCOUNTERH27:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3444: WARNING: Title underline too short. MHPMCOUNTERH28:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3444: WARNING: Title underline too short. MHPMCOUNTERH28:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3469: WARNING: Title underline too short. MHPMCOUNTERH29:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3469: WARNING: Title underline too short. MHPMCOUNTERH29:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3494: WARNING: Title underline too short. MHPMCOUNTERH30:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3494: WARNING: Title underline too short. MHPMCOUNTERH30:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3519: WARNING: Title underline too short. MHPMCOUNTERH31:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3519: WARNING: Title underline too short. MHPMCOUNTERH31:Upper 32 bits of Machine Hardware Performance Monitoring Counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3544: WARNING: Title underline too short. CYCLE:Cycle counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3544: WARNING: Title underline too short. CYCLE:Cycle counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3569: WARNING: Title underline too short. INSTRET:Instruction Retired counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3569: WARNING: Title underline too short. INSTRET:Instruction Retired counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3594: WARNING: Title underline too short. CYCLEH:Upper 32-bits of Cycle counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3594: WARNING: Title underline too short. CYCLEH:Upper 32-bits of Cycle counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3619: WARNING: Title underline too short. INSTRETH:Upper 32-bits of Instruction Retired counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3619: WARNING: Title underline too short. INSTRETH:Upper 32-bits of Instruction Retired counter Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3644: WARNING: Title underline too short. MVENDORID:Machine Vendor ID Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3644: WARNING: Title underline too short. MVENDORID:Machine Vendor ID Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3675: WARNING: Title underline too short. MARCHID:Machine Architecture ID Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3675: WARNING: Title underline too short. MARCHID:Machine Architecture ID Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3700: WARNING: Title underline too short. MIMPID:Machine Implementation ID Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3700: WARNING: Title underline too short. MIMPID:Machine Implementation ID Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3725: WARNING: Title underline too short. MHARTID:Machine Hardware Thread ID Register -------------------------- /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60x/csr.rst:3725: WARNING: Title underline too short. MHARTID:Machine Hardware Thread ID Register -------------------------- looking for now-outdated files... none found pickling environment... done checking consistency... /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst: WARNING: document isn't included in any toctree /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst: WARNING: document isn't included in any toctree /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/tristan/README.md: WARNING: document isn't included in any toctree /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/README.md: WARNING: document isn't included in any toctree /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst: WARNING: document isn't included in any toctree /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/riscv-isa/riscv-isa-manual/README.md: WARNING: document isn't included in any toctree /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/riscv-isa/riscv-isa-manual/dependencies/README.md: WARNING: document isn't included in any toctree /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/riscv-isa/riscv-isa-manual/docs-resources/README.md: WARNING: document isn't included in any toctree /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/riscv-isa/riscv-isa-manual/marchid.md: WARNING: document isn't included in any toctree /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Introduction.rst:148: WARNING: Citation [RVunpriv] is not referenced. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Introduction.rst:152: WARNING: Citation [RVpriv] is not referenced. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Introduction.rst:156: WARNING: Citation [RVdbg] is not referenced. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Introduction.rst:159: WARNING: Citation [RVcompat] is not referenced. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Introduction.rst:162: WARNING: Citation [AXI] is not referenced. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Introduction.rst:165: WARNING: Citation [CV-X-IF] is not referenced. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Introduction.rst:169: WARNING: Citation [OpenPiton] is not referenced. /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/01_cva6_user/Introduction.rst:178: WARNING: Citation [CLINT] is not referenced. done preparing documents... done copying assets... copying static files... done copying extra files... done copying assets: done writing output... [ 1%] 01_cva6_user/AXI_Interface writing output... [ 3%] 01_cva6_user/CSR_CV32A60AX writing output... [ 4%] 01_cva6_user/CSR_CV32A60AX_list writing output... [ 6%] 01_cva6_user/CSR_CV32A60X writing output... [ 7%] 01_cva6_user/CSR_CV32A60X_list writing output... [ 9%] 01_cva6_user/CSR_CV64A6_MMU writing output... [ 10%] 01_cva6_user/CSR_CV64A6_MMU_list writing output... [ 11%] 01_cva6_user/CSR_Cache_Control writing output... [ 13%] 01_cva6_user/CSR_Performance_Counters writing output... [ 14%] 01_cva6_user/CV32A6_Control_Status_Registers writing output... [ 16%] 01_cva6_user/CV64A6_Control_Status_Registers writing output... [ 17%] 01_cva6_user/CVA6_user_guide writing output... [ 19%] 01_cva6_user/CVX_Interface_Coprocessor writing output... [ 20%] 01_cva6_user/Compiler_Command_Lines writing output... [ 21%] 01_cva6_user/Core_Integration writing output... [ 23%] 01_cva6_user/Custom_Instructions writing output... [ 24%] 01_cva6_user/Interfaces writing output... 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[100%] riscv-isa/riscv-isa-manual/marchid /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/tristan/README.md:3: WARNING: None:any reference target not found: ./verif-spec/verification_specifications.adoc /home/docs/checkouts/readthedocs.org/user_builds/openhw-group-cva6-user-manual/checkouts/latest/docs/04_cv32a65x/tristan/README.md:5: WARNING: None:any reference target not found: ./tandem-verification/tandem.adoc generating indices... genindex done writing additional pages... search done copying images... [ 2%] 01_cva6_user/images/jade_design_automation_logo.png copying images... [ 4%] 01_cva6_user/rtype_format.png copying images... [ 6%] 02_cva6_requirements/images/cva6_scope.png copying images... [ 8%] 03_cva6_design/_static/mmu_in_out.png copying images... [ 10%] 03_cva6_design/_static/mmu_major_blocks.png copying images... [ 12%] 03_cva6_design/_static/mmu_control_flow.png copying images... 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[ 74%] 03_cva6_design/_static/branch_prediction.png copying images... [ 76%] 05_cva6_apu/_static/test_harness.png copying images... [ 78%] 05_cva6_apu/_static/ariane.png copying images... [ 80%] 05_cva6_apu/_static/axi_adapter.png copying images... [ 82%] 05_cva6_apu/_static/axi2mem.png copying images... [ 84%] 05_cva6_apu/_static/dm_top_slave.png copying images... [ 86%] 05_cva6_apu/_static/clint.png copying images... [ 88%] 05_cva6_apu/_static/bootrom.png copying images... [ 90%] 05_cva6_apu/_static/dram.png copying images... [ 92%] 05_cva6_apu/_static/sram.png copying images... [ 94%] 05_cva6_apu/_static/apb_uart.png copying images... [ 96%] 05_cva6_apu/_static/plic.png copying images... [ 98%] 05_cva6_apu/_static/plic_top.png copying images... [100%] 05_cva6_apu/_static/timer.png dumping search index in English (code: en)... done dumping object inventory... done build succeeded, 650 warnings. The HTML pages are in ../_readthedocs/html.